gs8662dt10bgd-450i GSI Technology, gs8662dt10bgd-450i Datasheet - Page 24

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gs8662dt10bgd-450i

Manufacturer Part Number
gs8662dt10bgd-450i
Description
72mb Sigmaquad-ii+tm Burst Of 4 Sram
Manufacturer
GSI Technology
Datasheet
JTAG Port Recommended Operating Conditions and DC Characteristics
JTAG Port AC Test Conditions
Notes:
1.
2.
Rev: 1.00 5/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Input Under/overshoot voltage must be –1 V < Vi < V
V
0 V ≤ V
Output Disable, V
The TDO output driver is served by the V
I
I
I
I
OHJ
OLJ
OHJC
OLJC
ILJ
= + 2 mA
Output reference level
= –2 mA
≤ V
Input reference level
= –100 uA
= +100 uA
Input high level
Input slew rate
Input low level
IN
Parameter
IN
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
≤ V
≤ V
ILJn
DDn
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
Test Port Output CMOS High
Test Port Output CMOS Low
OUT
Test Port Input High Voltage
Test Port Input Low Voltage
= 0 to V
Parameter
DDn
DD
Conditions
supply.
V
DD
1 V/ns
V
0.2 V
V
DD
DD
– 0.2 V
/2
/2
DDn
24/29
+1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC.
Symbol
GS8662DT07/10/19/37BD-450/400/350/333/300
V
V
V
I
V
V
I
V
I
INHJ
OHJC
INLJ
OLJC
OLJ
OHJ
OLJ
IHJ
ILJ
TDO
V
V
0.7 * V
DD
DD
–300
Min.
–0.3
–1
–1
– 0.2
– 0.1
DD
* Distributed Test Jig Capacitance
JTAG Port AC Test Load
0.3 * V
V
V
DD
DD
Max.
100
0.2
0.1
1
1
/2
+0.3
DD
50Ω
© 2011, GSI Technology
Unit
uA
uA
uA
V
V
V
V
V
V
30pF
Notes
*
5, 6
5, 7
5, 8
5, 9
1
1
2
3
4

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