mt9jsf12872pz Micron Semiconductor Products, mt9jsf12872pz Datasheet - Page 21
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mt9jsf12872pz
Manufacturer Part Number
mt9jsf12872pz
Description
Ddr3 Sdram Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT9JSF12872PZ.pdf
(25 pages)
Table 22: Configuration Register Bit Descriptions (Continued)
PDF: 09005aef83b4fcd7
jsf9c128_256x72pz.pdf – Rev. A 07/09
10:9
Bit
6
7
8
Description
Alarm window lock bit
0: Alarm trips are not locked and can be changed
1: Alarm trips are locked and cannot be changed
Critical trip lock bit
0: Critical trip is not locked and can be changed
1: Critical trip is locked and cannot be changed
Shutdown mode
0: Enabled
1: Shutdown
Hysteresis enable
00: Disable
01: Enable at 1.5°C
10: Enable at 3°C
11: Enable at 6°C
1GB, 2GB (x72, ECC, SR) 240-Pin Halogen-Free DDR3 RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
21
Notes
The shutdown mode is a power-saving mode that dis-
ables the temperature sensor.
When enabled, a hysteresis is applied to temperature
movement around the trip points (see Figure 4
(page 22)). As an example, if the hysteresis register
is enabled to a delta of 6°C, the preset trip points will
toggle when the temperature reaches the program-
med value. These values will reset when the tempera-
ture drops below the trip points minus the set
hysteresis level. In this case, this would be critical tem-
perature minus 6°C.
The hysteresis is applied to both the above alarm win-
dow and the below alarm window bits found in the
read-only temperature register (see Table 23
(page 22)). EVENT# is also affected by this register.
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