mt9jsf12872pz Micron Semiconductor Products, mt9jsf12872pz Datasheet - Page 17
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mt9jsf12872pz
Manufacturer Part Number
mt9jsf12872pz
Description
Ddr3 Sdram Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT9JSF12872PZ.pdf
(25 pages)
SM Bus Slave Subaddress Decoding
PDF: 09005aef83b4fcd7
jsf9c128_256x72pz.pdf – Rev. A 07/09
The interrupt mode enables software to reset EVENT# after a critical temperature thresh-
old has been detected. Threshold points are set in the configuration register by the user.
This mode triggers the critical temperature limit and both the MIN and MAX of the tem-
perature window.
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and only returns to the logic HIGH state when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode, and the critical EVENT# cannot be
cleared through software.
The temperature sensor’s physical address differs from the SPD EEPROM’s physical ad-
dress: binary 0011 for A0, A1, A2, and RW#, where A2, A1, and A0 are the three slave
subaddress pins and the RW# bit is the READ/WRITE flag.
If the slave base address is fixed for the temperature sensor/SPD EEPROM, then the
pins set the subaddress bits of the slave address, enabling the devices to be located any-
where within the eight slave address locations. For example, they could be set from 30h
to 3Eh.
1GB, 2GB (x72, ECC, SR) 240-Pin Halogen-Free DDR3 RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
17
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