mt9v032 aptina, mt9v032 Datasheet - Page 8

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Pin Descriptions
Table 3:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
48-Pin LLCC
Numbers
29
10
11
23
25
28
30
31
32
33
47
24
22
26
20
21
15
16
17
18
19
27
41
42
43
44
45
46
8
9
2
3
4
5
Pin Descriptions
Only pins D
SER_DATAOUT_N
BYPASS_CLKIN_N
SHFT_CLKOUT_N
SER_DATAOUT_P
BYPASS_CLKIN_P
SHFT_CLKOUT_P
SER_DATAIN_N
SER_DATAIN_P
FRAME_VALID
S_CTRL_ADR0
S_CTRL_ADR1
STFRM_OUT
LINE_VALID
EXPOSURE
STLN_OUT
STANDBY
LED_OUT
Symbol
RESET#
SYSCLK
PIXCLK
D
D
D
D
D
D
D
D
D
D
RSVD
S
SCLK
OUT
DATA
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OE
0 through D
5
6
7
8
9
4
3
2
1
0
OUT
9 may be tri-stated.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
Connect to D
Serial data in for stereoscopy (differential negative). Tie to 1kΩ
pull-up (to 3.3V) in non-stereoscopy mode.
Serial data in for stereoscopy (differential positive). Tie to D
non-stereoscopy mode.
Input bypass shift-CLK (differential negative). Tie to 1KΩ pull-up
(to 3.3V) in non-stereoscopy mode.
Input bypass shift-CLK (differential positive). Tie to D
stereoscopy mode.
Rising edge starts exposure in slave mode.
Two-wire serial interface clock. Connect to V
even when no other two-wire serial interface peripheral is
attached.
D
Asynchronous reset. All registers assume defaults.
Two-wire serial interface data. Connect to V
even when no other two-wire serial interface peripheral is
attached.
Output in master mode
phase; input in slave mode.
Output in master mode
phase; input in slave mode.
Asserted when D
Asserted when D
Parallel pixel data output 5.
Parallel pixel data output 6.
Parallel pixel data output 7.
Parallel pixel data output 8
Parallel pixel data output 9.
LED strobe output.
Parallel pixel data output 4.
Parallel pixel data output 3.
Parallel pixel data output 2.
Parallel pixel data output 1.
Parallel pixel data output 0.
Pixel clock out. D
Output shift CLK (differential negative).
Output shift CLK (differential positive).
Serial data out (differential negative).
Two-wire serial interface slave address bit 3.
Two-wire serial interface slave address bit 5.
Shut down sensor operation for power saving.
Master clock (26.6 MHz).
Serial data out (differential positive).
OUT
9
enable pad, active HIGH.
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
GND
.
OUT
OUT
OUT
data is valid.
data is valid.
is valid on rising edge of this clock.
—
—
start line sync to drive slave chip in-
start frame sync to drive a slave chip in-
Description
Aptina reserves the right to change products or specifications without notice.
DD
DD
©2005 Aptina Imaging Corporation. All rights reserved.
with 1.5K resistor
with 1.5K resistor
GND
Pin Descriptions
in non-
GND
in
Note
1
2