mt9v032 aptina, mt9v032 Datasheet - Page 68

• Manufacturer Part Number: mt9v032
• Description: 1/3-inch Wide-vga Cmos Digital Image Sensor
• Manufacturer: aptina

Appendix A – Serial Configurations
Configuration of Sensor for Stand-Alone Serial Output with Internal PLL
Figure 46:
PDF: 6538045704/Source:2194051501
MT9V022_DS - Rev. C 9/10 EN
Stand-Alone Topology
1. Power up sensor.
2. Enable LVDS driver (set R0xB3[4]= 0).
3. De-assert LVDS power-down (set R0xB1[1] = 0.
4. Issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0.
5. Force sync patterns for the deserializer to lock (set R0xB5[0] = 1).
6. Stop applying sync patterns (set R0xB5[0] = 0).
With the LVDS serial video output, the deserializer can be up to 8 meters from the
sensor. The serial link can save on the cabling cost of 14 wires (D
FRAME_VALID, PIXCLK, GND). Instead, just three wires (two serial LVDS, one GND) are
sufficient to carry the video signal.
In this configuration, the internal PLL generates the shift-clk (x12). The LVDS pins
SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked
at approximately the same system clock frequency).
Figure 46 shows how a standard off-the-shelf deserializer (National Semiconductor
DS92LV1212A) can be used to retrieve the standard parallel video signals of D
LINE_VALID and FRAME_VALID.
Typical configuration of the sensor:
If necessary:
BYPASS_CLKIN
SER_DATAIN
LVDS
LVDS
Sensor
69
SER_DATAOUT
MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor
8-bit configuration shown
LVDS
8
DS92LV1212A
PIXEL
FRAME_VALID
LINE_VALID
LVDS
SHIFT_CLKOUT
2
CLK
Appendix A – Serial Configurations
Aptina reserves the right to change products or specifications without notice.
26.6 MHz
26.6 MHz
Osc.
Osc.
8 meters (maximum)
©2005 Aptina Imaging Corporation. All rights reserved.
OUT
[9:0], LINE_VALID,
OUT
(9:0),