hys64t128000eu-3s-c2 Qimonda, hys64t128000eu-3s-c2 Datasheet - Page 4

• Manufacturer Part Number: hys64t128000eu-3s-c2
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Qimonda

1.2
The Qimonda HYS[64/72]T[128/256]0x0EU–[25F/2.5/3/3S]–
C2 module family are unbuffered DIMM modules “UDIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 256M × 64 (2GB) and as
ECC modules
density, intended for mounting into 240-pin connector
sockets.
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400E–555–12–G0" where 6400E
Rev. 0.51, 2007-12
12032007-I9KE-FFWO
Product Type
PC2-6400-555
HYS72T128000EU–25F–C2
HYS64T128000EU–25F–C2
HYS72T256020EU–25F–C2
HYS64T256020EU–25F–C2
PC2-6400-666
HYS72T128000EU–2.5–C2
HYS64T128000EU–2.5–C2
HYS72T256020EU–2.5–C2
HYS64T256020EU–2.5–C2
PC2-5300-444
HYS72T128000EU–3–C2
HYS64T128000EU–3–C2
HYS72T256020EU–3–C2
HYS64T256020EU–3–C2
PC2-5300-555
HYS72T128000EU–3S–C2
HYS64T128000EU–3S–C2
HYS72T256020EU–3S–C2
HYS64T256020EU–3S–C2
means Unbuffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency =5,
Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced on
the Raw Card "G".
1)
in 256M × 72 (2GB) in organization and
Description
Compliance Code
1GB 1Rx8 PC2–6400E–555–12–F0
1GB 1Rx8 PC2–6400U–555–12–D0
2GB 2R×8 PC2–6400E–555–12–G0
2GB 2R×8 PC2–6400U–555–12–E0
1GB 1Rx8 PC2–6400E–666–12–F0
1GB 1Rx8 PC2–6400U–666–12–D0
2GB 2R×8 PC2–6400E–666–12–G0
2GB 2R×8 PC2–6400U–666–12–E0
1GB 1Rx8 PC2–5300E–444–12–F0
1GB 1Rx8 PC2–5300U–444–12–D0
2GB 2R×8 PC2–5300E–444–12–G0
2GB 2R×8 PC2–5300U–444–12–E0
1GB 1Rx8 PC2–5300E–555–12–F0
1GB 1Rx8 PC2–5300U–555–12–D0
2GB 2R×8 PC2–5300E–555–12–G0
2GB 2R×8 PC2–5300U–555–12–E0
2)
4
Ordering Information for RoHS Compliant Products
The memory array is designed with 1 Gbit Double-Data-Rate-
Two (DDR2) Synchronous DRAMs. Decoupling capacitors
are mounted on the PCB board. The DIMMs feature serial
presence detect based on a serial E
2-pin I
configuration data and are write protected; the second
128 bytes are available to the customer.
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3/3S]–C2
2
C protocol. The first 128 bytes are programmed with
Description
1 Ranks, ECC
1 Ranks, Non-ECC
2 Ranks, ECC
2 Ranks, Non-ECC
1 Ranks, ECC
1 Ranks, Non-ECC
2 Ranks, ECC
2 Ranks, Non-ECC
1 Ranks, ECC
1 Ranks, Non-ECC
2 Ranks, ECC
2 Ranks, Non-ECC
1 Ranks, ECC
1 Ranks, Non-ECC
2 Ranks, ECC
2 Ranks, Non-ECC
Unbuffered DDR2 SDRAM Modules
Advance Internet Data Sheet
2
SDRAM Technology
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
PROM device using the
TABLE 2