hys64t128000eu-3s-c2 Qimonda, hys64t128000eu-3s-c2 Datasheet - Page 10

• Manufacturer Part Number: hys64t128000eu-3s-c2
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Qimonda

Rev. 0.51, 2007-12
12032007-I9KE-FFWO
Ball No.
167
168
Data Strobe Bus
7
16
28
37
84
93
105
114
46
6
15
27
36
83
92
104
113
45
Data Mask Signals
125
134
146
155
202
211
223
232
164
EEPROM
120
Name
CB6
NC
CB7
NC
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
SCL
Pin
Type
I/O
NC
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
—
SSTL
—
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
CMOS
Function
Check Bit 6
Note: ECC type module only
Not Connected
Note: ECC type module only
Check Bit 7
Note: ECC type module only
Not Connected
Note: Non-ECC module
Data Strobe Bus 8:0
The data strobes, associated with one data byte, sourced with data transfers.
In Write mode, the data strobe is sourced by the controller and is centered in
the data window. In Read mode the data strobe is sourced by the DDR2
SDRAM and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to
registers programmed appropriately.
Note: See block diagram for corresponding DQ signals
Complement Data Strobe Bus 8:0
Note: See block diagram for corresponding DQ signals
Data Mask Bus 8:0
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is LOW but
blocks the write operation if it is HIGH. In Read mode, DM lines have no effect.
Note: See block diagram for corresponding DQ M signals
Serial Bus Clock
This signal is used to clock data into and out of the SPD EEPROM.
10
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3/3S]–C2
Unbuffered DDR2 SDRAM Modules
V
Advance Internet Data Sheet
SS
and DDR2 SDRAM mode