hys64t128000eu-3s-c2 Qimonda, hys64t128000eu-3s-c2 Datasheet - Page 3

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hys64t128000eu-3s-c2

Manufacturer Part Number
hys64t128000eu-3s-c2
Description
240-pin Unbuffered Ddr2 Sdram Modules
Manufacturer
Qimonda
Datasheet
1
This chapter gives an overview of the 240-pin Unbuffered DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
• 240-Pin PC2-6400 and PC2-5300 DDR2 SDRAM memory
• Two rank 256M × 64, 256M × 72 and one rank 128M × 64,
• 2GB, 1GB Modules built with 1 Gbit DDR2 SDRAMs in
• Standard Double-Data-Rate-Two Synchronous DRAMs
• All speed grades faster than DDR2-400 comply with
• Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
Rev. 0.51, 2007-12
12032007-I9KE-FFWO
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
modules.
128M × 72 module organization and 128M × 8 chip
organization
chipsize packagesPG-TFBGA-60 .
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
DDR2-400 timing specifications.
Length (8 & 4).
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Features
Overview
CL4
CL5
CL6
DDR2
PC2
f
f
f
f
t
t
t
t
CK3
CK4
CK5
CK6
RCD
RP
RAS
RC
–25F
–800D
–6400D
5–5–5
200
266
400
12.5
12.5
45
57.5
3
• Auto Refresh (CBR) and Self Refresh
• Auto Refresh for temperatures above 85 °C
• Programmable self refresh rate via EMRS2 setting.
• Programmable partial array refresh via EMRS2 settings.
• DCC enabling via EMRS2 setting.
• All inputs and outputs SSTL_1.8 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
• Serial Presence Detect with E
• UDIMM and EDIMM Dimensions (nominal): 30 mm high,
• Based on standard reference layouts Raw Cards ’D’, 'E',
• RoHS compliant products
–800E
–6400E
6–6–6
200
266
333
400
15
15
45
60
–2.5
Termination (ODT)
133.35 mm wide
’F’ and 'G'
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3/3S]–C2
–3
–667C
–5300C
4–4–4
200
333
333
12
12
45
57
Unbuffered DDR2 SDRAM Modules
Advance Internet Data Sheet
1)
2
–3S
–667D
–5300D
5–5–5
200
266
333
15
15
45
60
PROM
Performance Table
TABLE 1
t
REFI
MHz
MHz
MHz
MHz
ns
ns
ns
ns
Unit
t
CK
= 3.9 µs.

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