hys64t128021hdl-3-b Infineon Technologies Corporation, hys64t128021hdl-3-b Datasheet - Page 11

• Manufacturer Part Number: hys64t128021hdl-3-b
• Description: 200-pin So-dimm Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 6
Pin or Ball No.
158
160
174
176
179
181
189
191
180
182
192
194
Data Strobe Signals
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
Data Mask Signals
10
26
52
67
130
147
170
185
EEPROM
Data Sheet
Pin Configuration of SO-DIMM (cont’d)
Name
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
11
Function
Data Bus 63:0
Data Strobe Bus 7:0
The data strobes, associated with one data byte,
sourced with data transfers. In Write mode, the data
strobe is sourced by the controller and is centered in
the data window. In Read mode the data strobe is
sourced by the DDR2 SDRAM and is sent at the
leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint
of respective DQS and DQS. If the module is to be
operated in single ended strobe mode, all DQS
signals must be tied on the system board to
DDR2 SDRAM mode registers programmed
appropriately.
Data Mask Bus 7:0
The data write masks, associated with one data byte.
In Write mode, DM operates as a byte mask by
allowing input data to be written if it is LOW but blocks
the write operation if it is HIGH. In Read mode, DM
lines have no effect.
HYS64T[32/64/128]xxxHDL-[2.5/…/5]-B
Pin Configurations and Block Diagrams
SO-DIMM DDR2 SDRAM Module
05122005-2TKP-OM7N
Rev 1.00, 2005-06
V
SS
and