m470l1624bt0 Samsung Semiconductor, Inc., m470l1624bt0 Datasheet - Page 8

• Manufacturer Part Number: m470l1624bt0
• Description: 128mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
AC OPERATING TEST CONDITIONS
Input/Output CAPACITANCE
M470L1624BT0
AC Operating Conditions
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Input reference voltage for Clock
Input signal maximum peak swing
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Input capacitance(A
Input capacitance(CKE
Input capacitance( CS
Input capacitance( CLK
Data & DQS input/output capacitance(DQ
Input capacitance(DM
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
IH
/V
Parameter/Condition
IX
IL
is expected to equal 0.5*V
Parameter
)
0
Parameter
~ A
0
0
~DM
0
0
)
)
, CLK
1 1
, BA
8
)
1
Output
)
0
~ BA
(V
DD
1
,RAS,CAS, WE )
Output Load Circuit (SSTL_2)
=2.5V, V
0
DDQ
~DQ
(V
DD
Z0=50
of the transmitting device and must track variations in the DC level of the same.
63
DDQ
=2.5V, V
C
)
LOAD
=2.5V, T
=30pF
V
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
tt
DDQ
=0.5*V
A
Symbol
= 25
=2.5V, T
V
C
C
C
C
C
C
REF
OUT
R
IN1
IN2
IN3
IN4
IN5
See Load Circuit
DDQ
T
=50
VREF + 0.31
0.7
0.5*VDDQ-0.2
+0.3 1/V
C
0.5 * V
200pin DDR SDRAM SODIMM
, f=1MHz)
V
=0.5*V
Value
V
REF
A
1.5
V
= 0 to 70
REF
Min
tt
DDQ
REF
DDQ
Min
-0.3 1
29
29
26
30
8
8
C
)
0.5*VDDQ+0.2
VREF - 0.31
VDDQ+0.6
Max
Rev. 0.2 Dec. 2001
Max
34
34
30
32
9
9
Unit
V
V
V
V
V
Unit
V
V
V
V
Unit
pF
pF
pF
pF
pF
pF
Note
Note
3
3
1
2