m470l1624bt0 Samsung Semiconductor, Inc., m470l1624bt0 Datasheet - Page 10

• Manufacturer Part Number: m470l1624bt0
• Description: 128mb Ddr Sdram Module
• Manufacturer: Samsung Semiconductor, Inc.

1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
4. A write command can be applied with t
5. For registered DIMMs, t
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Autoprecharge write recovery +
Precharge time
M470L1624BT0
but system performance (bus turnaround) will degrade accordingly.
jitter due to crosstalk (t
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
Parameter
64Mb, 128Mb
256Mb
JIT
CL
(crosstalk)
and t
CH
are
) on the DIMM.
RCD
45% of the period including both the half period jitter (t
Symbol
tPDEX
tXSNR
tXSRD
tWPST
tDIPW
tMRD
tREFI
tQHS
satisfied after this command.
tDAL
tDH
tQH
tDS
tHP
or tCHmin
(tWR/tCK)
(tRP/tCK)
-TCA2(DDR266A)
tCLmin
-tQHS
1.75
15.6
Min
200
tHP
0.5
0.5
7.5
7.8
0.4
15
75
+
Max
0.75
0.6
-
-
or tCHmin
(tWR/tCK)
(tRP/tCK)
-TCB0(DDR266B)
tCLmin
-tQHS
1.75
15.6
Min
200
tHP
200pin DDR SDRAM SODIMM
0.5
0.5
7.5
7.8
0.4
15
75
+
Max
0.75
0.6
-
-
JIT(HP)
(tWR/tCK)
or tCHmin
(tRP/tCK)
-TCA0 (DDR200)
tCLmin
-tQHS
15.6
Min
200
tHP
0.6
0.6
7.8
0.4
16
10
80
) of the PLL and the half period
2
+
Rev. 0.2 Dec. 2001
Max
0.8
0.6
-
-
Unit
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
us
us
ns
ns
ns
Note
7,8,9
7,8,9
11
4
1
1
5
3