mt16jtf25664ay-1g1 Micron Semiconductor Products, mt16jtf25664ay-1g1 Datasheet - Page 6

• Manufacturer Part Number: mt16jtf25664ay-1g1
• Description: 2gb, 4gb X64, Dr 240-pin Ddr3 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

General Description
Fly-By Topology
Serial Presence-Detect Operation
PDF: 09005aef82b22503/Source: 09005aef82b224f4
JTF16C_256_512x64AY.fm - Rev. A 7/07 EN
The MT16JTF25664AY and MT16JTF51264AY DDR3 SDRAM modules are high-speed,
CMOS, dynamic random-access 2GB and 4GB memory modules organized in a x64
configuration. These DDR3 SDRAM modules use internally configured 8-bank (1Gb and
2Gb) DDR3 SDRAM devices.
DDR3 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially an 8n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR3 SDRAM module effectively consists of a single
8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR3 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR3 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
DDR3 modules utilize faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. To ensure the best possible signal quality the clock
and command/address busses have been routed in a fly-by topology, where each clock
and address pin on each DRAM is connected to a single trace and terminated (rather
than a tree structure, where the termination is off the module near the connector).
Inherent to fly-by topology, the timing skew between the clock and DQS signals can be
easily accounted for by utilizing the write leveling feature of DDR3.
DDR3 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
module, permanently disabling hardware write protect.
2GB, 4GB (x64, DR) 240-Pin DDR3 SDRAM UDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2007 Micron Technology, Inc. All rights reserved.
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