mt16jtf25664ay-1g1 Micron Semiconductor Products, mt16jtf25664ay-1g1 Datasheet - Page 4

• Manufacturer Part Number: mt16jtf25664ay-1g1
• Description: 2gb, 4gb X64, Dr 240-pin Ddr3 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef82b22503/Source: 09005aef82b224f4
JTF16C_256_512x64AY.fm - Rev. A 7/07 EN
DQS0#–DQS7#
RAS#, CAS#,
DQS0–DQS7
CKE0, CKE1
DQ0–DQ63
CK0, CK0#,
DM0–DM7
CK1, CK1#
BA0–BA2
SA0–SA2
Symbol
S0#, S1#
A0–A14
V
RESET#
V
V
ODT0
ODT1
REF
WE#
REF
SDA
DDSPD
V
SCL
V
V
NC
DD
TT
SS
DQ
CA
Pin Description
Supply Power supply: 1.5V ±0.075V.
Supply Serial EEPROM positive power supply: +3.0V to +3.6V.
Supply Reference voltage: DQ, DM. V
Supply Reference voltage: Command, address, and control. V
Supply Ground.
Supply Termination voltage: Used for address, command, control, and clock nets. V
Input Address inputs: Provide the row address for ACTIVE commands and the column address and
Input Bank address inputs: BA0, BA1 define to which device bank an ACTIVE, READ, WRITE, or
Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled
Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
Input Data input mask: DM is an input mask signal for write data. Input data is masked when DM is
Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR3
Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
Input Reset: An active LOW CMOS input referenced to V
Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM address
Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer
Type
I/O
I/O
I/O
–
auto precharge bit for READ/WRITE commands to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine whether the
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA. A12 is sampled during READ and WRITE commands to
determine if burst chop (on-the-fly) will be performed. The address inputs also provide the op-
code during mode register command set
PRECHARGE command is being applied. BA0, BA1 define which mode register, including MR, EMR,
EMR(2), and EMR(3), is loaded during the LOAD MODE command.
on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/
DQS#) is referenced to the crossings of CK and CK#.
circuitry on the DDR3 SDRAM.
sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS7
pins.
SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS# and DM. The
ODT input will be ignored if disabled via the LOAD MODE command.
The reset pin input receiver is a CMOS input and is defined as a rail-to-rail signal with a DC HIGH ≥
0.8 x V
desertion are asynchronous. System applications will most likely be unterminated, heavily loaded,
and have very slow slew rates. A slow slew rate receiver design is recommended along with
implementing on-chip noise filtering to prevent false triggering (RESET# assertion minimum pulse
width is 100ns).
With both inputs HIGH, all outputs of the register(s) are disabled except for CKE and ODT. CKE,
ODT, and chip select remain in previous state when both outputs are HIGH.
range.
to and from the module.
Data input/output: Bidirectional data bus.
Data strobe: Output with read data, input with write data for source synchronous operation.
Edge-aligned with read data, center-aligned with write data.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the SPD EEPROM on the module.
No connect: These pins should be left unconnected.
DD
Q and DC LOW ≤ 0.2 x V
2GB, 4GB (x64, DR) 240-Pin DDR3 SDRAM UDIMM
DD
DD
/2.
Q (1.20V for HIGH and 0.30V for LOW). RESET# assertion and
4
.
A0–A13 (2GB) A0–A14 (4GB).
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
SS
and not referenced to V
DD
/2.
©2007 Micron Technology, Inc. All rights reserved.
REF
DD
CA or V
/2.
REF
DQ.