mt16vddf6464ay-40b Micron Semiconductor Products, mt16vddf6464ay-40b Datasheet - Page 9
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mt16vddf6464ay-40b
Manufacturer Part Number
mt16vddf6464ay-40b
Description
512mb, 1gb X64, Dr 184-pin Ddr Sdram Udimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT16VDDF6464AY-40B.pdf
(11 pages)
Table 10:
PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5
DDF16C64_128x64A.fm - Rev. B 11/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock
cycle; V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active;
changing twice per clock cycle; Address and other control inputs changing
once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
Address and control inputs change only during active READ or WRITE
commands
CK =
RC =
t
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK =
CK =
t
IN
RC =
= V
t
t
REF
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
t
RAS (MAX);
I
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
CK =
CK =
DD
for DQ, DQS, and DM
t
CK =
Specifications and Conditions – 1GB
t
t
Notes:
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
t
CK (MIN); I
OUT
t
CK =
= 0mA
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
in I
t
CK (MIN); DQ, DM, and DQS inputs
OUT
DD
t
RC =
2P (CKE LOW) mode.
= 0mA; Address and control inputs
t
RC (MIN);
t
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
RC =
t
CK =
t
t
REFC =
REFC = 7.8125µs
t
t
RC (MIN);
t
CK =
CK (MIN);
9
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
Electrical Specifications
©2007 Micron Technology, Inc. All rights reserved
1,280
1,520
1,560
1,600
5,520
3,640
-40B
880
720
960
176
80
80
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA