mt16vddf6464ay-40b Micron Semiconductor Products, mt16vddf6464ay-40b Datasheet - Page 8

• Manufacturer Part Number: mt16vddf6464ay-40b
• Description: 512mb, 1gb X64, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

I
Table 9:
PDF: 09005aef82c34cfe/Source: 09005aef82c34cc5
DDF16C64_128x64A.fm - Rev. B 11/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-
down mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
per clock cycle; Address and other control inputs changing once per clock
cycle
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle;
t
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving
reads (BL = 4) with auto precharge;
and control inputs change only during active READ or WRITE commands
DD
CK =
RC =
RC =
CK =
IN
= V
Specifications
t
t
t
t
t
RAS (MAX);
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); I
CK =
REF
for DQ, DQS, and DM
t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
I
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
CK =
CK =
DD
t
CK =
OUT
Specifications and Conditions – 512MB
t
t
t
Notes:
CK =
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
= 0mA
t
CK (MIN); I
t
CK (MIN); DQ, DM, and DQS inputs changing twice
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
in I
OUT
DD
t
RC =
2P (CKE LOW) mode.
= 0mA; Address and control inputs
t
RC (MIN);
t
t
512MB, 1GB (x64, DR) 184-Pin DDR SDRAM UDIMM
RC =
CK =
t
t
REFC =
REFC = 7.8125µs
t
t
RC (MIN);
t
CK (MIN); Address
CK =
8
t
RFC (MIN)
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
1,112
1,392
1,120
1,632
1,592
4,160
3,792
-40B
960
640
Electrical Specifications
64
96
64
©2007 Micron Technology, Inc. All rights reserved
1,032
1,392
1,432
1,432
4,080
3,312
-335
800
480
960
64
96
64
1,192
1,232
1,232
3,760
2,832
-265
992
720
400
800
64
96
64
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA