mt18d836m-5-20x Micron Semiconductor Products, mt18d836m-5-20x Datasheet - Page 2

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mt18d836m-5-20x

Manufacturer Part Number
mt18d836m-5-20x
Description
Ecc-optimized Dram Simms
Manufacturer
Micron Semiconductor Products
Datasheet
NOT RECOMMENDED FOR NEW DESIGNS
EDO PAGE MODE (continued)
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates like FAST-PAGE-MODE
READs, except data will be held valid or become valid
after CAS# goes HIGH, as long as RAS# is held LOW.
(Refer to the MT4C4M4E8 DRAM data sheet for addi-
tional information on EDO functionality.)
JEDEC-DEFINED
PRESENCE-DETECT – MT9D436 (16MB)
4, 8 Meg x 36 ECC-Optimized DRAM SIMMs
DM65_2.p65 – Rev. 9/98
SYMBOL
PRD1
PRD2
PRD3
PRD4
FAST-PAGE-MODE modules have traditionally
PIN
67
68
69
70
Vss
Vss
Vss
NC
-5
Vss
NC
NC
NC
-6
2
REFRESH
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining
power and executing anyRAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so
that all 2,048 combinations of RAS# addresses are ex-
ecuted at least every 32ms, regardless of sequence.
The CBR REFRESH cycle will invoke the refresh counter
for automatic RAS# addressing.
JEDEC-DEFINED
PRESENCE-DETECT – MT18D836 (32MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
Returning RAS# and CAS# HIGH terminates a
ECC-OPTIMIZED DRAM SIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PIN
67
68
69
70
Vss
Vss
Vss
NC
-5
4, 8 MEG x 36
Vss
NC
NC
NC
-6
©1998, Micron Technology, Inc.

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