mt18d836m-5-20x Micron Semiconductor Products, mt18d836m-5-20x Datasheet

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mt18d836m-5-20x

Manufacturer Part Number
mt18d836m-5-20x
Description
Ecc-optimized Dram Simms
Manufacturer
Micron Semiconductor Products
Datasheet
NOT RECOMMENDED FOR NEW DESIGNS
DRAM
MODULE
FEATURES
• Four-CAS#, ECC-optimized configuration in a 72-
• 16MB (4 Meg x 36) and 32MB (8 Meg x 36)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
• 2,048-cycle refresh distributed across 32ms
• Extended Data-Out (EDO) PAGE MODE access
OPTIONS
• Timing
• Package
KEY TIMING PARAMETERS
PART NUMBERS
GENERAL DESCRIPTION
accessed, 16MB and 32MB solid-state memories orga-
nized in a x36 configuration. These modules are de-
signed for systems that utilize ECC and do not conduct
single-byte accesses. These modules do not support
parity functionality.
addressed through 20 address bits that are entered 10
bits (A0-A9) at a time. RAS# is used to latch the first 10
bits and CAS# the latter 10 bits. READ or WRITE cycles
are selected with the WE# input. A logic HIGH on WE#
dictates read mode, while a logic LOW on WE# dictates
write mode. During a WRITE cycle, data-in (D) is latched
4, 8 Meg x 36 ECC-Optimized DRAM SIMMs
DM65_2.p65 – Rev. 9/98
PART NUMBER
MT9D436M-x X
MT18D836M-x X 8 Meg x 36
x = speed
SPEED
pin, single in-line memory module (SIMM)
(CBR) and HIDDEN
50ns access
60ns access
72-pin SIMM
-5
-6
The MT9D436 X and MT18D836 X are randomly
During READ or WRITE cycles, each bit is uniquely
104ns
84ns
t
RC
CONFIGURATION FEATURES
4 Meg x 36
t
50ns
60ns
RAC
20ns
25ns
t
PC
25ns
30ns
t
AA
4 CAS#, ECC
4 CAS#, ECC
t
MARKING
13ns
15ns
CAC
-5
-6
M
MODE
EDO
EDO
t
10ns
CAS
8ns
1
MT9D436 X
MT18D836 X
For the latest data sheet revisions, please refer to the
Micron Web site:
by the falling edge of WE# or CAS#, whichever occurs
last. EARLY WRITE occurs when WE# goes LOW prior to
CAS# going LOW, and the output pin(s) remain open
(High-Z) until the next CAS# cycle.
EDO PAGE MODE
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back HIGH.
EDO provides for CAS# precharge time (
without the output data going invalid. This elimina-
tion of CAS# output control provides for pipelined
READs.
*32MB version only
NOTE: Symbols in parentheses are not used on these
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
10
11
12
13
14
15
16
17
18
EDO PAGE MODE is an accelerated FAST-PAGE-
1
2
3
4
5
6
7
8
9
1
ECC-OPTIMIZED DRAM SIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PIN ASSIGNMENT (Front View)
modules but may be used for other modules in this
product family. They are for reference only.
DQ19
DQ20
DQ21
DQ22
DQ1
DQ2
DQ3
DQ4
V
V
NC
A0
A1
A2
A3
A4
A5
A6
DD
SS
4 Meg x 36 (shown)
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 NC/RAS3#* 51
34
35
36
www.micron.com/datasheets
72-Pin SIMM
NC (A11)
8 Meg x 36
RAS2#
DQ23
DQ24
DQ25
DQ26
DQ27
DQ5
DQ6
DQ7
DQ8
DQ9
A10
V
A7
A8
A9
DD
36
37
38
39
40
41
42
43
44
45 NC/RAS1#* 63
46
47
48
49
50
52
53
54
37
4, 8 MEG x 36
CAS0#
CAS2#
CAS3#
CAS1#
RAS0#
DQ18
DQ36
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
WE#
V
NC
NC
SS
©1998, Micron Technology, Inc.
t
55
56
57
58
59
60
61
62
64
65
66
67
68
69
70
71
72
CP) to occur
DQ13
DQ31
DQ14
DQ32
DQ33
DQ15
DQ34
DQ16
DQ35
DQ17
PRD1
PRD2
PRD3
PRD4
V
V
NC
NC
DD
SS
72

Related parts for mt18d836m-5-20x

mt18d836m-5-20x Summary of contents

Page 1

... PART NUMBERS PART NUMBER CONFIGURATION FEATURES MT9D436M Meg x 36 MT18D836M Meg speed GENERAL DESCRIPTION The MT9D436 X and MT18D836 X are randomly accessed, 16MB and 32MB solid-state memories orga- nized in a x36 configuration. These modules are de- signed for systems that utilize ECC and do not conduct single-byte accesses ...

Page 2

... NOT RECOMMENDED FOR NEW DESIGNS EDO PAGE MODE (continued) FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO operates like FAST-PAGE-MODE READs, except data will be held valid or become valid after CAS# goes HIGH, as long as RAS# is held LOW. ...

Page 3

NOT RECOMMENDED FOR NEW DESIGNS DQ1 DQ1 - 4 WE# U1 CAS# CAS0# RAS0# RAS# A0–A10 OE# 11 CAS1# WE# DQ19 DQ1 - 4 WE# U6 CAS# CAS2# RAS2# RAS# OE# A0–A10 11 CAS3# A0–A10 V U1- U1-U9 ...

Page 4

NOT RECOMMENDED FOR NEW DESIGNS DQ1 DQ1 - 4 WE# CAS0# CAS# RAS0# RAS# A0–A10 OE# 11 CAS1# WE# DQ19 DQ1 - 4 WE# CAS2# CAS# RAS# RAS2# A0–A10 OE# 11 CAS3# A0–A10 DQ1 DQ1 - 4 WE# CAS# RAS# ...

Page 5

NOT RECOMMENDED FOR NEW DESIGNS ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply Relative Operating Temperature, T (ambient) ... 0°C to +70°C A Storage Temperature (plastic) ............ -55°C to +125°C Power Dissipation ................................................... 9W Short Circuit Output Current ...

Page 6

NOT RECOMMENDED FOR NEW DESIGNS CAPACITANCE PARAMETER Input Capacitance: A0-A10 Input Capacitance: WE# Input Capacitance: RAS0#-RAS3# Input Capacitance: CAS0#-CAS3# Input/Output Capacitance: DQ1-DQ36 AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER Access time ...

Page 7

NOT RECOMMENDED FOR NEW DESIGNS AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12 CHARACTERISTICS PARAMETER RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time WRITE ...

Page 8

... HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. = 2V. 21.Column address changed once each cycle. OH 22.16MB module values will be half of those shown MEG x 36 ECC-OPTIMIZED DRAM SIMMs t CP. t RCD (MAX) limit is no longer specified. ...

Page 9

NOT RECOMMENDED FOR NEW DESIGNS V IH RAS CRP V CAS ASR V IH ROW ADDR WE TIMING PARAMETERS -5 SYMBOL MIN ...

Page 10

NOT RECOMMENDED FOR NEW DESIGNS V IH RAS CRP CAS ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 SYMBOL MIN ...

Page 11

NOT RECOMMENDED FOR NEW DESIGNS V IH RAS CSH t CRP V CAS RAD t ASR t RAH V IH ADDR ROW WE OPEN ...

Page 12

NOT RECOMMENDED FOR NEW DESIGNS EDO-PAGE-MODE EARLY-WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR V ROW WE# V ...

Page 13

NOT RECOMMENDED FOR NEW DESIGNS EDO-PAGE-MODE READ-EARLY-WRITE CYCLE V IH RAS CRP t RCD V IH CAS RAD t ASR t RAH V IH ADDR ROW WE ...

Page 14

NOT RECOMMENDED FOR NEW DESIGNS V IH RAS CRP V CAS ASR V IH ADDR WE TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 15

NOT RECOMMENDED FOR NEW DESIGNS V IH RAS CRP V IH CAS ASR V IH ADDR WE RAS# V ...

Page 16

NOT RECOMMENDED FOR NEW DESIGNS V IH RAS CRP CAS ASR t RAH V IH ADDR ROW TIMING PARAMETERS -5 SYMBOL MIN MAX MIN t ...

Page 17

NOT RECOMMENDED FOR NEW DESIGNS .125 (3.18) TYP .250 (6.35) 1.75 (44.45) TYP PIN 1 .080 (2.03) .125 (3.18) TYP .250 (6.35) 1.75 (44.45) TYP PIN 1 .080 (2.03) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: ...

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