mt18jsf25672az Micron Semiconductor Products, mt18jsf25672az Datasheet - Page 4

• Manufacturer Part Number: mt18jsf25672az
• Description: 2gb, 4gb X72, Ecc, Dr 240-pin Ddr3 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 6: Pin Descriptions
PDF: 09005aef83606b46
jsf18c256_512x72az.pdf – Rev. B 5/09
RAS#, CAS#, WE#
DQS#[8:0]
DQS[8:0],
ODT[1:0]
DQ[63:0]
Symbol
CK#[1:0]
CKE[1:0]
DM[8:0]
CK[1:0],
A[13:0]
BA[2:0]
RESET#
SA[2:0]
CB[7:0]
S#[1:0]
SDA
SCL
(LVCMOS)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set. A[13:0] address the 1Gb DDR3 devices. A[14:0] address the 2Gb
DDR3 devices. A15 is needed to calculate parity on the command/address bus.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address in-
put signals are sampled on the crossing of the positive edge of CK and the negative
edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM.
Data input mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH, along with the input data, during a write access. DM is sam-
pled on both edges of the DQS. Although the DM pins are input-only, the DM loading
is designed to match that of the DQ and DQS pins.
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,
DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: An active LOW CMOS input referenced to Vss. The RESET# input receiver is a
CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × Vdd and DC LOW ≤ 0.2
× Vdd.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Presence-detect address inputs: These pins are used to configure the temperature
sensor/SPD EEPROM address range on the I
Serial clock for presence-detect: SCL is used to synchronize the communication to
and from the temperature sensor/SPD EEPROM.
Check bits: Data used for ECC.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out
of the temperature sensor/SPD EEPROM on the module on the I
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
2
C bus.
© 2009 Micron Technology, Inc. All rights reserved.
2
C bus.