mt18jsf25672ay-1g1 Micron Semiconductor Products, mt18jsf25672ay-1g1 Datasheet - Page 17
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mt18jsf25672ay-1g1
Manufacturer Part Number
mt18jsf25672ay-1g1
Description
2gb, 4gb X72, Ecc, Dr 240-pin Ddr3 Sdram Udimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT18JSF25672AY-1G1.pdf
(20 pages)
Figure 4:
Table 21:
Temperature Format
Temperature Trip Point Registers
Table 22:
PDF: 09005aef83014429/Source: 09005aef83014466
JSF18C256_512x72A.fm - Rev. C 5/08 EN
15
0
Condition
Clears
14
Sets
0
Hysteresis
Alarm Temperature Lower Boundary Register (Address: 0x02)
Hysteresis
Above window bit
Below window bit
13
0
Notes:
MSB
12
1. T
2. T
3. Hyst is the value set in the hysteresis bits of the configuration register.
The temperature trip point registers and temperature readout register use a
“2’s complement” format to enable negative numbers. The least significant bit (LSB) is
equal to 0.0625°C or 0.25°C depending on which register is referenced. As an example,
assuming an LSB of 0.0625°C:
• A value of 0x018C would equal 24.75°C
• A value of 0x06C0 would equal 108°C
• A value of 0x1E74 would equal –24.75°C
The upper and lower temperature boundary registers are used to set the maximum and
minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in
the register will always report zero.
Temperature
T
T
Gradient
H
L
11
H
L
Falling
Rising
2
1
is the value set in the alarm temperature lower boundary trip register.
is the value set in the alarm temperature upper boundary trip register.
Below Alarm Window Bit
10
Alarm window upper boundary temperature
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
9
Critical Temperature
8
T
L
Bit
- Hyst
17
T
L
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6
Temperature
5
Gradient
Falling
Rising
T
Above Alarm Window Bit
H
-
4
Hyst
Electrical Specifications
3
3
©2008 Micron Technology, Inc. All rights reserved
T
Critical Temperature
L
-
LSB
Hyst
2
T
H
RFU
T
- Hyst
1
H
RFU
0