mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 9
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mt18lsdf6472y-133
Manufacturer Part Number
mt18lsdf6472y-133
Description
512mb X72, Ecc, Sr 168-pin Sdram Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT18LSDF6472Y-133.pdf
(26 pages)
Burst Type
Figure 4:
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
Mode Register Definition Diagram
The ordering of accesses within a burst is determined by BL, the burst type and the start-
ing column address, as shown in Table 6.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
M8
0
-
M9
0
1
M7
M12, M11, M10 = “0, 0, 0”
0
-
to ensure compatibility
Reserved
with future devices.
Programmed Burst Length
Single Location Access
12
Write Burst Mode
Defined
M6-M0
Program
A12
-
Reserved
11
A11
10
Operating Mode
Standard Operation
All other states reserved
A10
WB
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
9
A9
9
Op Mode
8
A8
7
A7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CAS Latency
6
A6
5
A5
4
A4
M3
BT
0
1
3
A3
M2
M6
Mode Register Definition
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
Burst Length
2
A2
M1
M5
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
M0
M4
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
A1
©2001 Micron Technology, Inc. All rights reserved.
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Interleaved
Burst Type
Sequential
1
2
4
8
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8