mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 18
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mt18lsdf6472y-133
Manufacturer Part Number
mt18lsdf6472y-133
Description
512mb X72, Ecc, Sr 168-pin Sdram Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT18LSDF6472Y-133.pdf
(26 pages)
PLL and Register Specifications
Table 13:
Table 14:
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
Register
Parameter
Operating clock frequency
Input duty cycle
Cycle to cycle jitter
Static phase offset
SSC induced skew
Output to output skew
bit pattern by
JESD82-2
SSTL
Register Timing Requirements and Switching Characteristics
PLL Clock Driver Timing Requirements And Switching Characteristics
Symbol
f
t
t
clock
t
t
pd1
pd2
t
su
w
h
Notes: 1. SSC = Spread spectrum clock. The use of SSC synthesizers on the system motherboard will
Propagation delay, Single rank
2. Skew is defined as the total clock skew between any two outputs and is therefore speci-
Propagation delay, Dual rank
reduce EMI.
fied as a maximum only.
Clock frequency
(CK to output)
(CK to output)
Pulse duration
Parameter
Setup time
Hold time
Symbol
t
t
t
f
t
JIT
SK
SSC
t
CK
DC
∅
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
CC
O
18
Data before CK HIGH
Data after CK HIGH
CK, HIGH or LOW
50pF to GND and
30pF to GND and
Condition
50Ω to V
50Ω to V
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Min
-150
-75
50
44
DD
0°C ≤ T
–
–
= +3.3V ±0.3V
TT
TT
PLL and Register Specifications
A
≤ 55°C
Max
140
150
150
150
55
75
V
DD
0°C ≤ T
Min
150
1.4
0.7
3.3
.75
.75
= +3.3V ±0.3V
©2001 Micron Technology, Inc. All rights reserved.
Units
MHz
A
%
ps
ps
ps
ps
≤ 55°C
Max
240
3.5
2.4
-
-
-
Notes
1, 2
Units
MHz
ns
ns
ns
ns
ns