mt18lsdf6472y-133 Micron Semiconductor Products, mt18lsdf6472y-133 Datasheet - Page 8

• Manufacturer Part Number: mt18lsdf6472y-133
• Description: 512mb X72, Ecc, Sr 168-pin Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Initialization
Mode Register Definition
Burst Length
PDF: 09005aef80a2e32f/Source: 09005aef80d04a5a
SDF18C64x72G.fm - Rev. E 9/05 EN
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Once power is
applied to V
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, Command Inhibit or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one Command Inhibit or NOP com-
mand having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO
refresh cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
The mode register is used to define the specific mode of operation of the SDRAM device.
This definition includes the selection of BL, a burst type, CL, an operating mode and a
write burst mode, as shown in the Mode Register Definition Diagram. The mode register
is programmed via the LOAD MODE REGISTER command and will retain the stored
information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify BL, M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify CL, M7 and M8 specify the operating mode, M9 specifies the
write burst mode, and M10 and M11 are reserved for future use. A12 (M12) is undefined,
but should be driven LOW during loading of mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Read and write accesses to the SDRAM are burst oriented, with the BL being program-
mable, as shown in Figure 4 on page 9. BL determines the maximum number of column
locations that can be accessed for a given READ or WRITE command. BL of 1, 2, 4, or 8
locations are available for both the sequential and the interleaved burst types, and a full-
page burst is available for the sequential type. The full-page burst is used in conjunction
with the BURST TERMINATE command to generate arbitrary BL.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is effectively
selected. All accesses for that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached, as shown in Figure 6 on page 10. The
block is uniquely selected by A1–A9, A11 when BL = 2; A2–A9, A11 when BL = 4; and by
A3–A9, A11 when BL is = 8. The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 6.
DD
and V
DD
Q (simultaneously) and the clock is stable (stable clock is
512MB (x72, ECC, SR): 168-PIN SDRAM RDIMM
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
Initialization