mt18hts25672pky-53e Micron Semiconductor Products, mt18hts25672pky-53e Datasheet - Page 4

• Manufacturer Part Number: mt18hts25672pky-53e
• Description: 2gb, 4gb X72, Dr 244-pin Ddr2 Mini-rdimm
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef82218d23/Source: 09005aef82218d00
HTS18C256_512x72K.fm - Rev. B 9/07 EN
RDQS0–RDQS8
ODT0, ODT1
RAS#, CAS#,
DQS0–DQS8
CKE0, CKE1
DQ0–DQ63
DM0–DM8/
CK0, CK0#
BA0–BA2
SA0–SA2
CB0–CB7
Symbol
S0#, S1#
E
A0–A15
V
P
RR
V
WE#
SDA
DDSPD
V
AR
V
SCL
DD
_O
REF
DD
_I
Q
N
UT
Pin Descriptions
(open drain)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Output
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA2) or all device banks (A10 HIGH). The address inputs also provide the op-
code during a LOAD MODE command. A0–A13 (2GB) and A0–A14 (4GB). A0–A15 are
connected for parity.
Bank address inputs: BA0–BA2 define to which device bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0–BA2 define which mode register, including MR,
EMR, EMR (2), and EMR (3), is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
circuitry on the DDR2 SDRAM.
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS,
DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Parity bit for the address and control bus. Non-parity version is not used.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when S# is registered HIGH. S# provides for external rank
selection on systems with multiple ranks. S# is considered part of the command code.
Presence-detect address inputs: These pins are used to configure the presence-detect
device.
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
Data input/output: Bidirectional data bus.
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
Check bits.
Data input mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH, along with that input data, during a write access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of
DQ and DQS pins. If RDQS is disabled, DQS9–DQS17 become DM0–DM8 and DQS9#–DQS17#
are not used.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data
into and out of the presence-detect portion of the module.
Parity error found on the address and control bus. Non-parity version is not used.
Power supply: 1.8V ±0.1V.
DQ power supply: 1.8V ±0.1V.
Serial EEPROM positive power supply: +1.7V to +3.6V.
SSTL_18 reference voltage (V
DD
2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
4
/2).
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2006 Micron Technology, Inc. All rights reserved.