mt18hts25672rhy-53e Micron Semiconductor Products, mt18hts25672rhy-53e Datasheet - Page 9

• Manufacturer Part Number: mt18hts25672rhy-53e
• Description: 2gb, 4gb X72, Ecc, Dr 200-pin Ddr2 Sdram Sordimm
• Manufacturer: Micron Semiconductor Products

Table 10:
PDF: 09005aef828665bd/Source: 09005aef828665a3
HTS18C_256_512x72RH.fm - Rev. B 5/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
t
commands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
control and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
RC =
RCD =
CK =
RAS =
RP =
RAS =
CK =
DD
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
t
t
t
t
RP (I
RC (I
CK (I
CK (I
t
t
t
OUT
OUT
RAS MAX (I
RAS MAX (I
RCD (I
DD
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
DDR2 I
Values shown for MT47H512M8THM DDR2 SDRAM only and are computed from values specified in the
4Gb TwinDie (512 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus
),
DD
t
t
RAS =
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
DD
t
t
),
),
CK =
DD
RC (I
t
RAS MIN (I
t
t
DD
RP =
RP =
t
CK =
Specifications and Conditions – 4GB
), AL = 0;
DD
t
CK (I
t
t
),
RP (I
RP (I
t
CK (I
t
RRD =
DD
DD
DD
DD
),
DD
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
CK =
t
); CKE is HIGH, S# is HIGH between valid
); CKE is HIGH, S# is HIGH between valid
RC =
), AL = 0;
); REFRESH command at every
), AL =
t
RRD (I
t
CK (I
t
RC (I
2GB, 4GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
t
DD
RCD (I
DD
t
),
DD
CK =
),
t
t
DD
RCD =
),
CK =
t
t
DD
RAS =
CK =
t
t
4W
RAS =
CK =
t
CK (I
) - 1 ×
t
CK (I
t
t
t
RCD (I
CK =
OUT
CK (I
t
t
DD
t
CK (I
RAS MAX (I
t
CK =
RAS MIN (I
9
t
DD
),
CK (I
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
= 0mA; BL = 4,
DD
t
CK (I
DD
),
DD
t
),
CK (I
); CKE is
DD
); CKE is
DD
t
);
RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
); CKE
DD
);
),
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
Electrical Specifications
1,017
1,422
1,422
1,647
2,637
3,177
-667
144
567
657
360
612
144
90
©2007 Micron Technology, Inc. All rights reserved.
1,062
1,242
1,656
2,457
2,772
-53E
927
144
576
567
315
522
144
90
1,062
1,197
1,665
2,367
2,772
-40E
927
144
585
522
270
477
144
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA