mt18htf25672py Micron Semiconductor Products, mt18htf25672py Datasheet - Page 13

• Manufacturer Part Number: mt18htf25672py
• Description: Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Table 12: DDR2 I
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) com-
ponent data sheet
PDF: 09005aef80e5e752
htf18c64_128_256x72py.pdf - Rev. F 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switch-
ing
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
=
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads, I
t
is HIGH between valid commands; Address bus inputs are stable during dese-
lects; Data bus inputs are switching
RCD =
CK (I
CK (I
DD
t
RP (I
),
DD
DD
t
RAS =
OUT
DD
DD
DD
OUT
t
); CKE is LOW; Other control and address bus inputs
),
RCD (I
DD
),
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus
t
RC =
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
), AL = 0;
RP =
RP =
t
RAS MIN (I
DD
t
RC (I
); CKE is HIGH, S# is HIGH between valid commands; Address
t
t
RP (I
RP (I
DD
DD
t
CK =
DD
DD
),
Specifications and Conditions (Die Revision A) – 2GB
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
); CKE is HIGH, S# is HIGH between valid commands;
CK =
t
RRD =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid com-
t
CK (I
t
CK (I
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
t
DD
RRD (I
),
DD
DD
DD
t
CK =
t
), AL = 0;
RC =
); REFRESH command at every
), AL =
DD
),
t
CK (I
t
RC (I
t
RCD =
t
RCD (I
t
DD
CK =
DD
),
),
t
DD4W
t
CK =
t
t
RCD (I
DD
t
RAS =
CK =
t
RAS =
t
CK (I
CK =
) - 1 ×
t
CK =
t
CK (I
t
DD
DD
CK (I
t
OUT
t
CK =
t
t
RAS MAX (I
t
CK (I
RAS MIN (I
); CKE is HIGH, S#
CK =
),
13
t
CK (I
DD
t
= 0mA; BL = 4,
DD
RAS =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
),
t
DD
CK (I
),
t
t
DD
CK (I
); CKE is
RAS =
t
RC =
);
t
RFC (I
t
DD
RAS
t
DD
DD
DD
CK =
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE
t
),
t
),
);
RC
RAS
DD
t
RP
)
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
I
I
I
DD2N
DD3N
DD4R
DD2P
DD3P
DD0
DD1
DD5
DD6
DD7
-667
1620
1800
1080
1260
2880
2880
4680
5400
126
990
720
180
126
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
1440
1710
2340
2610
4500
5220
-53E
126
738
810
540
180
990
126
Specifications
1260
1440
1980
1980
3960
4680
-40E
126
630
720
450
180
810
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA