mt18htf25672py Micron Semiconductor Products, mt18htf25672py Datasheet - Page 10

• Manufacturer Part Number: mt18htf25672py
• Description: Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 10: DDR2 I
Values shown for MT47H64M4 DDR2 SDRAM only and are computed from values specified in the 256Mb (64 Meg x 4)
component data sheet
PDF: 09005aef80e5e752
htf18c64_128_256x72py.pdf - Rev. F 3/10 EN
Parameter
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL (I
(I
switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
trol and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
=
are switching; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads,
I
t
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
DD
RAS =
OUT
OUT
RC (I
DD
DD
DD
t
RP (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
); CKE is LOW; Other control and address bus inputs are stable;
),
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
Specifications
t
RP =
), AL = 0;
DD
t
),
RAS MIN (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
t
RRD =
t
RP (I
t
DD
DD
CK =
t
RRD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
t
CK (I
Specifications and Conditions – 512MB
DD
t
CK =
),
DD
t
t
RCD =
DD
DD
CK =
),
t
CK (I
), AL = 0;
), AL =
t
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
RC =
t
CK (I
t
DD
DD4W
RCD (I
t
); REFRESH command at every
RC (I
t
RCD (I
DD
t
CK =
),
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
RAS =
),
DD
t
t
CK (I
) - 1 ×
RAS =
t
CK =
t
t
RAS MAX (I
CK =
DD
t
CK =
t
t
),
CK (I
RAS MIN (I
t
CK =
t
t
CK (I
RAS =
t
CK (I
t
OUT
CK =
t
DD
t
CK (I
CK =
10
t
DD
);
CK
= 0mA; BL = 4, CL =
DD
DD
t
t
),
t
DD
RAS MAX (I
CK =
CK (I
),
t
DD
),
t
CK (I
); CKE is HIGH, S#
RAS =
t
RC =
t
),
RP =
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RFC (I
DD
t
t
CK (I
RCD =
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE is
t
t
); CKE is
t
RC (I
RAS MAX
RP (I
DD
DD
DD
t
) inter-
),
RCD
DD
),
DD
t
RC =
t
),
RP
);
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
DD7
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
1440
1620
2880
2700
3060
4320
-53E
630
630
450
108
720
90
90
Specifications
1350
1530
2250
2070
2970
4140
-40E
450
540
360
108
540
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA