m69ar024b STMicroelectronics, m69ar024b Datasheet - Page 8

• Manufacturer Part Number: m69ar024b
• Description: 16 Mbit 1m X16 1.8v Supply, Asynchronous Psram
• Manufacturer: STMicroelectronics

M69AR024B
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see
2., Operating
Power Up Sequence
Because the internal control logic of the
M69AR024B needs to be initialized, the following
power-on procedure must be followed before the
memory is used:
Read Mode
The device is in Read mode when:
The time taken to enter Read mode (t
or t
was the last to reach the appropriate level.
Data out (DQ15-DQ0) may be indeterminate
during t
be valid during t
Write Mode
The device is in Write mode when
8/28
BLQV
–
–
–
–
–
–
–
–
ELQX
Apply power and wait for V
Wait 300µs while driving both Chip Enable
signals (E1 and E2) High
Write Enable (W) is High and
Output Enable (G) Low and
Upper Byte Enable (UB) or Lower Byte
Enable (LB) is Low, or both
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
Write Enable (W) is Low and
Upper Byte Enable (UB) or Lower Byte
Enable (LB) is Low, or both
) depends on which of the above signals
, t
Modes).
GLQX
AVQV
and t
.
BLQX
, but data will always
CC
ELQV
to stabilize
, t
Table
GLQV
The Write cycle begins just after the event (the fall-
ing edge) that causes the last of these conditions
to become true (t
The Write cycle is terminated by the earlier of a ris-
ing edge on Write Enable (W) or Chip Enable (E1).
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB) or Lower Byte Enable (LB) is Low), then
Write Enable (W) will return the outputs to high im-
pedance within t
be taken to avoid bus contention in this type of op-
eration. Data input must be valid for t
the rising edge of Write Enable (W), for t
fore the rising edge of Chip Enable (E1), or for t
VBH
whichever occurs first, and remain valid for t
t
Standby Mode
The device is in Standby mode when:
The input/output buffers and the decoding/control
logic are switched off, but the dynamic array con-
tinues to be refreshed. In this mode, the memory
current consumption, I
remains valid.
Deep Power-down Mode
The device is in Deep Power-down mode when:
EHDZ
–
–
–
–
before the rising edge of Byte Enable (LB,UB),
or t
the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
Chip Enable (E1) is High and
Chip Enable (E2) is High
Chip Enable (E2) is Low
BHDZ
.
WLQZ
AVWL
of its falling edge. Care must
SB
or t
, is reduced, and the data
AVEL
or t
AVBL
DVWH
).
DVEH
before
WHDZ
be-
D-
,