k4t51043qb-gce6 Samsung Semiconductor, Inc., k4t51043qb-gce6 Datasheet - Page 29

• Manufacturer Part Number: k4t51043qb-gce6
• Description: 512mb B-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

512Mb B-die DDR2 SDRAM
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combi-
5. Definitions for IDD
IDD4W
IDD4R
IDD5B
IDD6
IDD7
nations of EMRS bits 10 and 11.
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
Operating burst write current;
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
t CK = t CK(IDD), t RAS = t RASmax(IDD), t RP = t RP(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Burst auto refresh current;
t CK = t CK(IDD);
Refresh command at every t RFC(IDD) interval;
CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V;
CKE ≤ 0.2V;
Other control and address bus inputs are
FLOATING;
Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = t RCD(IDD)-1* t CK(IDD);
t CK = t CK(IDD), t RC = t RC(IDD), t RRD = t RRD(IDD),
t RCD = 1* t CK(IDD);
CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
- Refer to the following page for detailed timing conditions
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
masks or strobes.
Normal
Low Power
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Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
Preliminary