k4t51043qb-gce6 Samsung Semiconductor, Inc., k4t51043qb-gce6 Datasheet - Page 15

• Manufacturer Part Number: k4t51043qb-gce6
• Description: 512mb B-die Ddr2 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

512Mb B-die DDR2 SDRAM
3.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
3.3 DM Truth Table
Notes:
Write enable
Write inhibit
1. Used to mask write data, provided coincident with the corresponding data
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set operations or
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh
14. CKE must be maintained high while the SDRAM is in OCD calibration mode .
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven high or
11. Minimum CKE high time is three clocks.; minimum CKE low time is three clocks.
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the t
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
Current State
Bank(s) Active
All Banks Idle
Power Down
Self Refresh
Name (Functional)
Read commands may be issued only after t
Precharge operations are in progress. See section 2.2.9 "Power Down" and 3.2.8 "Self Refresh Command" for a detailed list of
restrictions.
section 2.2.2.4.
requirements outlined in section 2.2.7.
low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1) ).
2
Previous Cycle
(N-1)
H
H
H
H
L
L
L
L
CKE
1
DM
Current Cycle
H
-
(N)
H
H
H
L
L
L
L
L
XSRD
1
(200 clocks) is satisfied.
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DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
RAS, CAS, WE, CS
Command (N)
REFRESH
Valid
DQs
X
Refer to the Command Truth Table
X
X
3
Precharge Power Down Entry
Active Power Down Entry
Maintain Power-Down
Maintain Self Refresh
Self Refresh Entry
Power Down Exit
Self Refresh Exit
Action (N)
Note
1
1
3
Rev. 0.91 (Sep. 2003)
DDR2 SDRAM
Preliminary
XSNR
4, 8, 10,11,13
4,8,10,11,13
4, 8, 11,13
6, 9, 11,13
11, 13, 15
11, 15
Notes
4, 5,9
period.
7