lrs1387 Sharp Microelectronics of the Americas, lrs1387 Datasheet
lrs1387
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lrs1387 Summary of contents
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... Flash + 8M (x16) SRAM LRS1387 Date Aug. 8. 2001 ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please ...
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Description ...
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... Description The LRS1387 is a combination memory organized as 4,194,304 x16 bit flash memory and 524,288 x16 bit static RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon ...
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Pin Configuration INDEX (TOP View) 3 ...
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Pin Address Inputs (Common F Address Inputs (Flash) F S-A Address Input (SRAM) 17 F-CE Chip Enable Input (Flash) S-CE , S-CE Chip Enable Inputs ...
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Truth Table (1) 3.1 Bus Operation Flash SRAM Notes F-CE Read 3,5 Output 5 Standby L Disable Write 2,3,4,5 Read 5 Output Standby 5 H Disable Write 5 Read 5,6 Reset Power Output 5,6 X Down Disable Write ...
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Simultaneous Operation Modes Allowed with Four Planes IF ONE Read PARTITION IS: Read ID Array Read Array X X Read Read Status X X Read Query X X Word Program X X Page Buffer X ...
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Block Diagram F-A , F F-CE F-OE F-WE F-WP F-RST S-A 17 S-CE 1 S-CE 2 S-OE S-WE S-LB S- ...
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Command Definitions for Flash Memory 5.1 Command Definitions Command Cycles Req’d Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) ...
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If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. ...
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Identifier Codes for Read Operation Manufacturer Code Manufacturer Code Device Code 64M Bottom Parameter Device Code Block is Unlocked Block is Locked Block Lock Configuration Code Block is not Locked-Down Block is Locked-Down Device Configuration Code Partition Configuration ...
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Functions of Block Lock and Block Lock-Down (1) State F- [000 (3) [001] [011 [100 (3) [101] ( [110] [111 Notes: 1. ...
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Block Locking State Transitions upon Command Write Current State DQ DQ State F-WP 1 [000 [001 [011 [100 [101 [110 ...
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Status Register Definition WSMS BESS BEFCES 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE ...
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SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ...
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PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in ...
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Memory Map for Flash Memory Bottom Parameter BLOCK NUMBER ADDRESS RANGE 134 32K-WORD 133 32K-WORD 132 32K-WORD 131 32K-WORD 130 32K-WORD 129 32K-WORD 128 32K-WORD 127 32K-WORD 126 32K-WORD 125 32K-WORD 124 32K-WORD 123 32K-WORD 122 32K-WORD 121 ...
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Absolute Maximum Ratings Symbol Parameter V Supply voltage CC V Input voltage IN T Operating temperature A T Storage temperature STG F-V F-V voltage PP PP Notes: 1. The maximum applicable voltage on any pins with respect to ...
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DC Electrical Characteristics Symbol Parameter I Input Load Current LI I Output Leakage Current LO I F-V Standby Current CCS CC F-V Automatic Power Savings CC I CCAS Current I F-V Reset Power-Down Current CCD CC Average ...
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Symbol Parameter I S-V Standby Current S-V Standby Current SB1 CC I S-V Operation Current CC1 CC I S-V Operation Current CC2 CC V Input Low Voltage IL V Input High Voltage IH V Output Low ...
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AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load 12.2 Read Cycle Symbol t Read Cycle Time AVAV t Address to ...
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Write Cycle (F-WE / F-CE Controlled) Symbol t Write cycle time AVAV F-RST High Recovery to F-WE (F-CE) Going Low PHWL PHEL F-CE (F-WE) Setup to F-WE (F-CE) Going Low ELWL WLEL ...
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Block Erase, Full Chip Erase, (Page Buffer) Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / 4K-Word Parameter Block ...
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Flash Memory AC Characteristics Timing Chart AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes or Query Code (A) 21 F-CE ( F-OE (G) ...
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AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks (A) 21 (A) 2 F-CE ( (G) F-OE V ...
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AC Waveform for Write Operations(F-WE / F-CE Controlled ...
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Reset Operations Symbol F-RST Low to Reset during Read t PLPH (F-RST should be low during power-up.) t F-RST Low to Reset during Erase or Program PLRH t F-V 2.7V to F-RST High VPH CC t F-V 2.7V ...
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AC Electrical Characteristics for SRAM 13.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle Symbol t Read ...
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Write Cycle Symbol t Write cycle time WC t Chip enable to end of write CW t Address valid to end of write AW t Byte select time BW t Address setup time AS t Write pulse width ...
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SRAM AC Characteristics Timing Chart Read Cycle Timing Chart Standby V IH Address S- S- S- ...
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Write Cycle Timing Chart (S-WE Controlled ...
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Write Cycle Timing Chart (S-CE Controlled ...
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Write Cycle Timing Chart (S-UB, S-LB Controlled ...
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Data Retention Characteristics for SRAM Symbol Parameter V Data Retention Supply voltage CCDR I Data Retention Supply current CCDR t Chip enable setup time CDR t Chip enable hold time R Notes 1. Reference value ...
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Notes This product is a stacked CSP package that a 64M (x16) bit Flash Memory and a 8M (x16) bit SRAM are assembled into. - Supply Power Maximum difference (between F-V - Power Supply and Chip Enable of ...
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Flash Memory Data Protection Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted ...
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Design Considerations 1. Power Supply Decoupling To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1µF ceramic capacitor connected between its F-V Low inductance capacitors should be placed ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t F-V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V ...
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... ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 ...