am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 7

• Manufacturer Part Number: am49pdl129bh85it
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
• Manufacturer: Meet Spansion Inc.

Flash AC Characteristics . . . . . . . . . . . . . . . . . . . 63
pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 75
December 16, 2003
Read-Only Operations – Am29PDL127H ............................... 63
Read-Only Operations – Am29PDL129H ............................... 63
Hardware Reset (RESET#) .................................................... 65
Erase and Program Operations .............................................. 66
Temporary Sector Unprotect .................................................. 71
Alternate CE#f1 Controlled Erase and Program Operations .. 73
Figure 13. Timing Diagram for Alternating
Between Pseudo SRAM and Flash................................................. 62
Figure 14. Read Operation Timings ................................................ 64
Figure 15. Page Read Operation Timings....................................... 64
Figure 16. Reset Timings ................................................................ 65
Figure 17. Program Operation Timings........................................... 67
Figure 18. Accelerated Program Timing Diagram........................... 67
Figure 19. Chip/Sector Erase Operation Timings ........................... 68
Figure 20. Back-to-back Read/Write Cycle Timings ....................... 69
Figure 21. Data# Polling Timings (During Embedded Algorithms).. 69
Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 70
Figure 23. DQ2 vs. DQ6.................................................................. 70
Figure 24. Temporary Sector Unprotect Timing Diagram ............... 71
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram .............................................................. 72
Figure 26. Flash Alternate CE#f1 Controlled Write (Erase/Program)
Operation Timings........................................................................... 74
A D V A N C E
Am49PDL127BH/Am49PDL129BH
I N F O R M A T I O N
Erase And Programming Performance . . . . . . . 80
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 80
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 80
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 80
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . 81
pSRAM Power on and Deep Power Down . . . . . 81
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 82
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 83
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 84
Read Cycle ............................................................................. 75
Write Cycle ............................................................................. 77
TLA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 83
Figure 27. Pseudo SRAM Read Cycle........................................... 75
Figure 28. Page Read Timing ........................................................ 76
Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 77
Figure 30. Pseudo SRAM Write Cycle—CE1#s Control ................ 78
Figure 31. Pseudo SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 79
Figure 32. Deep Power-down Timing............................................. 81
Figure 33. Power-on Timing........................................................... 81
Figure 34. Read Address Skew ..................................................... 82
Figure 35. Write Address Skew...................................................... 82
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