am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 17

• Manufacturer Part Number: am49pdl129bh85it
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
• Manufacturer: Meet Spansion Inc.

Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the OE# and appropriate CE#f1/CE#f2 (PDL129
only) pins to V
trol and for PDL129 select the lower (CE#f1) or upper
(CE#f2) halves of the device. OE# is the output control
and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the Flash AC Characteristics table for timing
specifications and to Figure 14 for the timing diagram.
I
tive current specification for reading array data.
Random Read (Non-Page Read)
Address access time (t
stable addresses to valid output data. The chip enable
access time (t
dresses and stable CE#f1 to valid data at the output
inputs. The output enable access time is the delay
from the falling edge of the OE# to valid data at the
output inputs (assuming the addresses have been sta-
ble for at least t
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. Address bits
A22–A3 (A21–A3 for PDL129) select an 8-word page,
and address bits A2–A0 select a specific word within
that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
The random or initial page access is t
subsequent page read accesses (as long as the loca-
tions specified by the microprocessor fall within that
page) are t
only) are deasserted (CE#f1=CE#f2=V
tion of CE#f1 or CE#f2 (PDL129 only) for subsequent
access has access time of t
CE#f1/CE#f2 (PDL129 only) selects the device and
OE# is the output control and should be used to gate
data to the output inputs if the device is selected. Fast
December 16, 2003
CC1
in the DC Characteristics table represents the ac-
IH
PACC
.
IL
ACC
. CE#f1 and CE#f2 are the power con-
CE
. When CE#f1 and CE#f2 (PDL129
) is the delay from the stable ad-
–t
OE
ACC
time).
) is equal to the delay from
ACC
A D V A N C E
or t
CE
IH
Am49PDL127BH/Am49PDL129BH
ACC
), the reasser-
. Here again,
or t
CE
and
I N F O R M A T I O N
page mode accesses are obtained by keeping
A22–A3 (A21–A3 for PDL129) constant and changing
A2 to A0 to select the specific word within that page.
Simultaneous Operation
In addition to the conventional features (read, pro-
gram, erase-suspend read, and erase-suspend pro-
gram), the device is capable of reading data from one
bank of memory while a program or erase operation is
in progress in another bank of memory (simultaneous
operation), The bank can be selected by bank ad-
dresses (A22–A20) (A21–A20 for PDL129) with zero
latency.
The simultaneous operation can execute multi-func-
tion mode in the same bank.
Bank A
Bank B
Bank C
Bank D
Bank
Bank C
Bank D
Bank A
Bank B
Bank
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
Word
Table 3. Bank Select (PDL129H)
Table 4. Bank Select (PDL127H)
CE#f1
Table 2. Page Select
0
0
1
1
CE#f2
1
1
0
0
A2
0
0
0
0
1
1
1
1
001, 010, 011
100, 101, 110
A22–A20
000
111
A1
00, 01, 10
01, 10, 11
A21–A20
0
0
1
1
0
0
1
1
11
00
A0
0
1
0
1
0
1
0
1
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