am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 65

• Manufacturer Part Number: am49pdl129bh85it
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
• Manufacturer: Meet Spansion Inc.

FLASH AC CHARACTERISTICS
Read-Only Operations – Am29PDL127H
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 18 for test specifications
Read-Only Operations – Am29PDL129H
Notes:
1.
2. See Figure 11 and Table 18 for test specifications
3. Valid CE#f1/CE#f2 conditions: (CE#f1= V
4. Valid CE#f1/CE#f2 transitions: (CE#f1= CE#f2= V
December 16, 2003
JEDEC
JEDEC
t
t
t
t
t
t
t
t
t
t
t
t
t
t
GHQZ
GHQZ
AVQV
ELQV
GLQV
EHQZ
AXQX
AVQV
ELQV
GLQV
EHQZ
AXQX
AVAV
AVAV
Not 100% tested.
(CE#f1= V
V
Parameter
Parameter
IL
, CE#f2=V
t
t
IH
Std.
t
Std.
t
t
t
PACC
PACC
t
t
t
t
OEH
t
t
t
t
OEH
ACC
t
t
ACC
t
t
RC
CE
OE
OH
RC
CE
OE
OH
, CE#f2=V
DF
DF
DF
DF
IH
) or (CE#f1= V
Description
Read Cycle Time (Note 1)
Address to Output Delay
Chip Enable to Output Delay
Page Access Time
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1, 3)
Output Enable to Output High Z (Notes 1, 3)
Output Hold Time From Addresses, CE#f1 or
OE#, Whichever Occurs First (Notes 3)
Output Enable Hold Time
(Note 1)
Description
Read Cycle Time (Note 1)
Address to Output Delay (Note 3)
Chip Enable to Output Delay (Note 4)
Page Access Time
Output Enable to Output Delay
Chip Enable to Output High Z (Notes 1, 5, 6)
Output Enable to Output High Z (Notes 1, 5)
Output Hold Time From Addresses, CE#f1/CE#f2
or OE#, Whichever Occurs First (Notes 5, 6)
Output Enable Hold Time
(Note 1)
IL
).
IH
, CE#f2=V
A D V A N C E
IL
IL
, CE#f2= V
).
Am49PDL127BH/Am49PDL129BH
IH
) to (CE#f1=
Read
Toggle and
Data# Polling
Read
Toggle and
Data# Polling
IH
) or
I N F O R M A T I O N
3. Measurements performed by placing a 50 ohm termination on the
5. Measurements performed by placing a 50 ohm termination on the
6. Valid CE#f1/CE#f2 transitions: (CE#f1= V
data pin with a bias of V
bus driven to V
data pin with a bias of V
bus driven to V
(CE#f1= V
CE#f1, OE# = V
CE#f1, OE# = V
Test Setup
Test Setup
OE# = V
OE# = V
IH
, CE#f2=V
CC
CC
IL
IL
/2 is taken as t
/2 is taken as t
IL
IL
IL
) to (CE#f1= CE#f2= V
CC
CC
/2. The time from OE# high to the data
/2. The time from OE# high to the data
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
Min
Min
DF
DF
.
.
Speed Options
Speed Options
66
65
65
65
25
25
66
65
65
65
25
25
IL
, CE#f2= V
16
16
10
16
16
10
5
0
5
0
IH
).
85
85
85
85
30
85
85
85
85
30
30
30
IH
) or
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
63