s71ns128ja0 Advanced Micro Devices, s71ns128ja0 Datasheet - Page 18

• Manufacturer Part Number: s71ns128ja0
• Description: Stacked Multi-chip Product Mcp , 128 Megabit 8 M X 16-bit And 64 Megabit 4 M X 16-bit , 110 Nm Cmos 1.8 Volt-only Simultaneous Read/write, Burst Mode Flash Memories With 16 Megabit 1 M X 16-bit Psram
• Manufacturer: Advanced Micro Devices

pSRAM CHARACTERISTICS
18
pSRAM Device Operation
pSRAM Read Access
pSRAM Write Access
Configuration Register Access
The access is performed in two stages. The first stage is address latching. The
first stage takes place between points A and B in timing diagram. At this stage,
the Chip Select (CS#) to the device is asserted. The random access is enabled
either from the point the address becomes stable, the falling edge of the AVD#
signal or from the falling edge of the last CS# signal.
The second stage is the read or write access. This takes place between points B
and C in timing diagram. In case of read access, the multiplexed address/ data
bus A/DQ[15-0] changes its direction. It is important to notice t
inant that the device gets into the read cycle since the address is available long
before the device output is enabled.
The read access (See Figures 5, 6) is initiated by applying the address to the mul-
tiplexed address/data bus A/DQ[15-0] and address bus A[19-16]. When the
address is stable, the device chip select (CS#) is set active low. At point A, the
AVD# signal is taken low and the latch becomes transparent. This allows the ad-
dress to be propagated to the memory array. The address is stable at the rising
edge of the AVD# signal. The AVD# signal goes high at point B in which the ad-
dress latch is completed. At this point the read cycle is entered. The OE# signal
is set active low. This changes the direction of the bus. The status of control sig-
nals UB# and LB# is set according to the access. Data is read at point C.
The write access (Figures
tiplexed address/data bus A/DQ[15-0] and the address bus A[19-16]. When the
address is stable, the device chip select (CS#) is asserted active low. At point A,
the AVD# signal is taken low and the latch becomes transparent. This allows the
address to be propagated to the memory array. The address is stable at the rising
edge of the AVD# signal. The AVD# signal goes high at point B in which the ad-
dress latch is completed. At this point, the second stage of the write process is
entered. Data is input to the multiplexed address/data bus. The WE# signal is set
low and control signals UB# and LB# are set according to the access.
A configuration register is needed to control the different modes of the RAM. The
configuration register consists of 16 bits and it can be accessed when LB# and
UB# signals are de-asserted. The AVD# signal is not used during configuration
access. Configuration registers read access is shown in Figure 3 and write ac-
cesses in Figure 4.
The configuration registers bits are specified in Table 7. Writing to bits 15 - 8,
does not change the device operation in normal mode.
7
and 8) is initiated by applying the address to the mul-
S71NS128JA0/S71NS064JA0
P r e l i m i n a r y
OE
when it is dom-
31136A1 February 5, 2004