s71ns128ja0 Advanced Micro Devices, s71ns128ja0 Datasheet
s71ns128ja0
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s71ns128ja0 Summary of contents
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... Hardware reset input (RESET#) — Hardware method to reset the device for reading array data CMOS compatible inputs and outputs Package — 48-ball Very Thin FBGA (S71NS128JA0) — 44-ball Very Thin FBGA (S71NS064JA0) Revision A Amendment 1 Issue Date February 5, 2004 PRELIMINARY = V ...
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... Max OE# Access Time Max Access Time ACC2 Max CE# Access Time Max OE# Access Time IACC ) BACC ) ACC ) ACC3 ) OE S71NS128JA0/S71NS064JA0 S71NS128JA0, S71NS064JA0 00, 10, 20 01, 11 MHz 54 MHz S29NS128J/00, S29NS064J/ 87 ...
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... Note: A22 available for 128 Mb Flash only 1. A15–A0 are multiplexed with DQ15–DQ0 indicates the highest order address bit. MAX February 5, 2004 31136A1 RDY CLK RESET# Flash Memory V PP CE# (S29NS128J OE# or WE# S29NS064J) A21 A22 16 Mb LB# UB# pSRAM CS# S71NS128JA0/S71NS064JA0 A/DQ15-A/DQ0 3 ...
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... A16 A20 AVD# NC CS# RESET A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 GND A/DQ5 A/DQ4 A/DQ11 A/DQ10 S71NS128JA0/S71NS064JA0 A10 A19 A17 A22/UB B10 A18 CE# GND C8 C9 C10 OE# A/DQ9 A/DQ8 D8 D9 D10 V A/DQ1 A/DQ0 CC NC ...
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... A16 A20 AVD# NC CS# RESET A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ2 GND A/DQ14 A/DQ5 A/DQ4 A/DQ11 A/DQ10 S71NS128JA0/S71NS064JA0 A10 A19 A17 UB B10 A18 CE# GND C8 C9 C10 OE# A/DQ9 A/DQ8 D8 D9 D10 V A/DQ1 A/DQ0 ...
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... accelerates programming; automatically places device in unlock bypass mode erase functions. Should *A22/UB# A21/LB# A20–A16 16 A/DQ15– A/DQ0 CLK CE# CS# OE# WE# RDY RESET# AVD *A22 available for 128Mb Flash only. S71NS128JA0/S71NS064JA0 , disables program and IL for all other conditions. IH 31136A1 February 5, 2004 ...
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... Very Thin Fine-Pitch BGA Lead (Pb)-Free Package pSRAM DENSITY Megabit (1M x 16-Bit) FLASH PROCESS TECHNOLOGY J = 110 nm Floating Gate Technology FLASH DENSITY 128 = 128 Megabit ( 16-Bit) 064 = 64 Megabit ( 16-Bit) Valid Combinations S71NS128JA0/S71NS064JA0 ° ° +85 C) ° ° +85 C), contact local 7 ...
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... Order Number S71NS128JA0BAW013 S71NS128JA0BFW013 S71NS128JA0BAW113 S71NS128JA0BFW113 S71NS128JA0BAW213 S71NS128JA0BFW213 S71NS064JA0BAW013 S71NS064JA0BFW013 S71NS064JA0BAW113 S71NS064JA0BFW113 S71NS064JA0BAW213 S71NS064JA0BFW213 Valid Combinations for BGA Package Package Marking Package 71NS128JA0BAW01 Pb-Free Compliant 71NS128JA0BFW01 Pb-Free 71NS128JA0BAW11 Pb-Free Compliant 71NS128JA0BFW11 Pb-Free 71NS128JA0BAW21 Pb-Free Compliant ...
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... PHYSICAL DIMENSIONS–S71NS128JA0 NLA048—48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA Package D A1 CORNER INDEX MARK 10 TOP VIEW A A1 SEATING PLANE SIDE VIEW PACKAGE NLA 048 JEDEC N/A 9. 10.95 mm NOM PACKAGE SYMBOL MIN NOM MAX A 1.05 --- 1.20 OVERALL THICKNESS A1 0.20 --- ...
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... WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. S71NS128JA0/S71NS064JA0 D1 A1 CORNER ...
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... February 5, 2004 31136A1 Revision Autoselect 0003h Contents Initial (ES) 712Eh EMLSI Initial (ES) 711Eh EMLSI Second (ES) 711Dh EMLSI Second (ES) 711Dh Micron S71NS128JA0/S71NS064JA0 Major Reason(s) for Change Initial release Initial release t and t Timing Update CSS AVDH t and t Timing Update CSS AVDH 11 ...
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... Table 3. NLA048 Connections C6–D6 A10–B10 C7–D7 A9–B9 C8–D8 A8–B8 C9–D9 A7–B7 C10–D10 A6–B6 On substrate S71NS128JA0/S71NS064JA0 Spansion Flash Description 128-Mbit 110nm Flash 16-Mbit pSRAM NLA048 A5–B5 A4–B4 A3–B3 A2–B2 A1–B1 NF2–NF5 NF17-NF20 ...
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... NF1 NF4 NF16 NF19 February 5, 2004 31136A1 Figure 1. NLA048 Daisy Chain Layout (Top View, Balls Facing Down) S71NS128JA0/S71NS064JA0 NF2 NF5 9 10 NF17 NF20 13 ...
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... Table 6. NLB044 Connections C6–D6 A10–B10 C7–D7 A9–B9 C8–D8 A8–B8 C9–D9 A7–B7 C10–D10 A6–B6 On substrate S71NS128JA0/S71NS064JA0 Spansion 64/16Mb MCP Part Number Description 64-Mbit 110nm Flash S71NS064JA0 16-Mbit pSRAM NLB044 A5–B5 A4–B4 A3–B3 A2–B2 A1– ...
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... NF1 NF3 February 5, 2004 31136A1 Figure 2. NLB044 Daisy Chain Layout (Top View, Balls Facing Down) S71NS128JA0/S71NS064JA0 NF2 9 10 NF4 15 ...
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... ≥ CS# V –0.2V, Other Inputs = 0~V CC S71NS128JA0/S71NS064JA0 Mode Power Deselected Standby Output Disabled Active Output Disabled Active Configuration Register Write Active Access Configuration Register Read Active Access Address Input Active Lower Byte Read Active ...
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... AVDH t CSS t ACC1 t ACC2 t ACC3 t ADOE UBLBA t BLZ t OLZ BHZ t OHZ t ACW1 t ACW2 t ACW3 t WRL S71NS128JA0/S71NS064JA0 Min Max Units ...
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... Figure 4. The configuration registers bits are specified in Table 7. Writing to bits does not change the device operation in normal mode and 8) is initiated by applying the address to the mul- S71NS128JA0/S71NS064JA0 when it is dom- OE 31136A1 February 5, 2004 ...
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... A/DQ15-0 CS# WE# LB#, UB#, OE# Figure 4. Configuration Register Write Access February 5, 2004 31136A1 Table 7. Configuration Register Definition 00 = Full array 01 = 1/2 array 10 = 1/4 array 11 = 1/8 array 00 = Internal temperature sensing Don't Care t ACC3 t OE Data Valid t ACC3 t WRL S71NS128JA0/S71NS064JA0 Remark Data Valid High 19 ...
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... AVDS AVDH Address Valid t ACC2 t OLZ ADOE t CSS t BLZ t UBLBA are continuously repeated for over 4 µ s, the device needs a normal read ACC at least once in every 4 µ s. ACC S71NS128JA0/S71NS064JA0 C Data Valid t OHZ BHZ ) IH C Data Valid t OHZ BHZ ) IH 31136A1 February 5, 2004 ...
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... CSS t ACW3 AVD t t AVDS AVDH Address Valid t ACW2 t WRL t CSS low CS#, low WE# and low UB# or LB#. A write begins at the last transition among S71NS128JA0/S71NS064JA0 C Data Valid Data Valid measured from the WRL 21 ...
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... Spansion, the Spansion logo, MirrorBit, and combinations thereof are registered trademarks of FASL LLC. ExpressFlash is a trademark of FASL LLC. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies S71NS128JA0/S71NS064JA0 31136A1 February 5, 2004 ...