hi-3200 Holt Integrated Circuits, Inc., hi-3200 Datasheet - Page 18

• Manufacturer Part Number: hi-3200
• Description: Avionics Data Management Engine / Arinc 429 - Can Bus Bridge
• Manufacturer: Holt Integrated Circuits, Inc.

A 1K x 8 block of memory located between 0x3000 and
0x33FF is reserved for a set of eight ARINC 429 received
data FIFOs. There is one FIFO for each ARINC 429
received data channel. Each FIFO can hold up to 32 ARINC
429 32-bit messages.
A look-up table driven filter defines which ARINC 429
messages are stored in each FIFO. The look-up table is
pre-loaded with a “1” for each bit position corresponding to
a selected channel / label combination. The look-up table is
located at memory address 0x7A00.
When a new ARINC 429 message is received that meets
the programmed conditions for acceptance (Enable look-
up table bit = “1”), it is written into the channel’s Receive
Data FIFO. The contents of the FIFO may be read by the
host CPU using dedicated FIFO read SPI Instructions.
The status of each channel’s FIFOs is monitored by three
FIFO status registers: FIFO NOT EMPTY, FIFO
THRESHOLD, and FIFO FULL. One bit of each register
reflects the current status of each FIFO.
ARINC 429 Received Data Log FIFO
ARINC 429 Received Data Enable Look-Up Table
ARINC 429 Received Data FIFO (x8)
0x7AFF
0x7AE0
0x7A3F
0x7A20
0x7A1F
ARINC 429
0x7A00
message
received
0 - 32 Messages (32-bits)
Filter Look-Up Table
Filter-Look-Up Table
Filter Look-Up Table
Channel 7
Channel 1
Channel 0
SPI Instruction
Data read by
Host CPU
HOLT INTEGRATED CIRCUITS
HI-3200, HI-3201
Label = 0xFF
Label = 0x0F
Label = 0x07
FIFO THRESHOLD
FIFO NOT EMPTY
18
The FIFOs are empty following Reset. All three status
registers are cleared. When an ARINC 429 message is
written to a FIFO, its FIFO NOT EMPTY bit is set to a “1”.
When the FIFO contains more than the user-defined
number of messages as programmed in the ARINC FIFO
THRESHOLD VALUE register, its FIFO THRESHOLD bit is
set. If the FIFO is allowed to accumulate 32 messages, its
FIFO FULL bit is set. Once a FIFO is full, subsequent
messages continue to be written to the FIFO, and the oldest
message is lost.
The user may generate an Interrupt by enabling one of the
three FIFO status register bits to assert the FLAG bit in the
Pending Interrupt Register. ARINC 429 Control Register
bits 1:0 select the condition to trigger the FLAG interrupt.
The FIFO feature is particularly useful if the application
wishes to accumulate sequential ARINC 429 messages of
the same label value before reading them. The regular
ARINC 429 receive data memory will, of course, overwrite
messages of the same label value if a new message is
received before the host CPU extracts the data.
ARXCn <1:0>
FIFO FULL
7
6
5
A FNEn
4
AFHFn
A FFn
Channels
3
Other
From
2
1
}
0
Select
Label = 0x01
Label = 0x08
Label = 0xF8
Label = 0x00
OR
FLAGn
PIR
FLAG