hi-3200 Holt Integrated Circuits, Inc., hi-3200 Datasheet - Page 14

• Manufacturer Part Number: hi-3200
• Description: Avionics Data Management Engine / Arinc 429 - Can Bus Bridge
• Manufacturer: Holt Integrated Circuits, Inc.

CANBTR1 cont.
HI-3200 Operational Status Information
The Master Status Register may be read at any time to determine the current operational state of the HI-3200:
Bit
5:0
Bit Name
7
6
5
4
3
2
1
0
MASTER STATUS REGISTER
(Address 0x800E)
READY
ACTIVE
SAFE
RAM BUSY
PROG
AUTOINIT
-
HI-3110
Name
TSEG1-3:0
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Default Description
Default Description
0
0
0
0
0
0
0
0
0
Time segment 1 length. Tseg1 = Prop Seg + Phase Seg 1 of the CAN protocol bit timing
specification. Bits TSEG1-3:0 specify the number of time quanta in Prop Seg + Phase Seg1.
Note: Not all combinations are valid since Prop Seg = Phase Seg1 >= Phase Seg2.
protocol states that the minimum number of Tq in a bit time shall be 8.
Note ARINC 825 states that the sample point shall not be less than 75% of the bit time. In this
case, TSeg1 should be a minimum of 5Tq for Phase Seg2 (TSeg2) = 2Tq and SJW = 1Tq.
TSEG2 bits <2:0>
etc.
This bit is high, when the READY output pin is high, indicating that the part is able to accept and
respond to host CPU SPI commands
This bit is high after RUN is asserted and the HI-3200 is in normal operating mode.
This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or auto-
initialization fail.
This is high during the time the RAM Integrity Check is running and RAM is clearing
Indicates that the HI-3200 is currently in the EEPROM programming cycle. Note that READY
stays low until the cycle is complete.
The HI-3200 is currently loading internal memory, registers and look-up tables from the Auto-
initialization EEPROM
Not used
The HI-3200 has detected the presence of an HI-3110 device connected to the CAN SPI
port.
initialization this bit is not updated in Mode 6 or 7.
0000: Not valid
0001: TSeg1 = 2 Tq clock cycles
0010: TSeg1 = 3 Tq clock cycles
1111: TSeg1 = 16 Tq clock cycles
Note:
HOLT INTEGRATED CIRCUITS
Only valid when RUN = 1 and CANTX and/or CANRX are enabled. After HI-3110
HI-3200, HI-3201
MSB
7
14
6
5
4
3
2
X
1
LSB
0
The CAN