s71gs256nc0bawak0 Meet Spansion Inc., s71gs256nc0bawak0 Datasheet - Page 194

• Manufacturer Part Number: s71gs256nc0bawak0
• Description: Stacked Multi-chip Product Mcp 256/128 Megabit 16/8m X 16-bit Cmos 3.0 Volt Vcc And 1.8 V Vio Mirrorbit Tm Uniform Sector Page-mode Flash Memory With 64/32 Megabit 4/2m X 16-bit 1.8v Psram
• Manufacturer: Meet Spansion Inc.

Note:Timing constraints when page mode is enabled.
Summary
194
Impact on Extended WRITE Operations
Modified timings are only required during extended WRITE operations (see
83
(t
minimum WRITE cycle time (t
is available for both a refresh operation and successful completion of the WRITE
operation.
CellularRAM products are designed to ensure that any possible bus timings do not
cause corruption of array data due to lack of refresh. The on-chip refresh circuitry
will only affect the required timings for WRITE operations (READs are unaffected)
performed in a system with a slow memory interface. The impact for WRITE op-
erations is that some of the timing parameters (t
modified timings are likely to have little or no impact when interfacing a Cellular-
RAM device with a low-speed memory bus.
WP
below). An extended WRITE operation requires that both the write pulse width
) and the data valid period (t
ADDRESS
LB#/UB#
DATA- I N
WE#
CE#
Figure 82. Extended Timing for t
Figure 83. Extended WRITE Operation
C E#
A d v a n c e
WC[MIN]
CellularRAM-2A
DW
t CEM or t TM > 4 µs
) will need to be lengthened to at least the
). These increased timings ensure that time
t
CEM
<
10µs
I n f o r m a t i o n
t WP > t WC (MIN)
t DW > t WC (MIN)
WP
, t
CEM
DW
) are lengthened. The
(2)
cellRAM_02_A0 December 15, 2004
Figure