am79c930 Advanced Micro Devices, am79c930 Datasheet - Page 56

• Manufacturer Part Number: am79c930
• Description: Pcnet-mobile Single-chip Wireless Lan Media Access Controller
• Manufacturer: Advanced Micro Devices

The following is a brief summary of the IEEE 1149.1
compatible
Am79C930 device:
Boundary Scan Circuit
The boundary scan test circuit uses five pins: TRST,
TCK, TMS, TDI, and TDO. These five pins are collec-
tively labeled the TAP. The boundary scan test circuit in-
cludes a finite state machine (FSM), an instruction
register, and a data register array. Internal pull-up resis-
tors are provided for the TDI and TMS pins. The TCK pin
must not be left unconnected.
Instruction Register and Decoding Logic
After H_RESET or S_RESET, the IDCODE instruction
is always loaded into the IEEE 1149.1 register. The de-
coding logic gives signals to control the data flow in the
DATA registers according to the current instruction.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch
are used for the SERIAL SHIFT STAGE and for the
PARALLEL OUTPUT STAGE, respectively.
There are four possible operation modes in the
BSR cell:
Other Data Registers
(1) BYPASS REGISTER (1 BIT)
(2) DEVICE ID REGISTER (32 BITS)
(3) INSCAN0
56
Instruction Name
1
2
3
4
AMD
ID_CODE
Reserved
SAMPLE
BYPASS
EXTEST
Capture
Shift
Update
System Function
test
functions
Instruction Code
0011–1110
implemented
0001
0010
1111
0000
P R E L I M I N A R Y
in
Reserved
Normal
Normal
Normal
Mode
the
Test
Am79C930
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power up or after H_RESET.
The TRST pin is supported in order to ensure that the
FSM is in the TEST_LOGIC_RESET state before test-
ing is begun.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), one
additional instruction (IDCODE) is provided as addi-
tional support for board level testing. All unused instruc-
tion decodes are reserved.
Device ID Register Contents:
This is an internal scan path for AMD internal
testing use.
Power Saving Modes
Power Down Function
The Am79C930 BIU includes five registers that are used
to invoke a power-down function that will support the
IEEE 802.11 (draft) specified power down by allowing
variable lengths of power-down and power-up time. The
registers include the Processor Interface Register
(MIR0), which contains the Power Down command bit, a
Power Down Length Count set of registers (MIR2,3,4),
and a Power Up Clock Timer (MIR1) register. The power
down sequence is executed by the firmware running
on the embedded 80188, either independently, or in
response to a request from the host. In the PCMCIA
Bits 31–28:
Bits 27–12:
Bits 11–1:
Bit 0:
Selected Data Register
Reserved
Bypass
BSR
BSR
ID
Version
Part Number (0010 1000 0101 0000)
Manufacturer ID. The 11 bit manufacturer
ID code for AMD is 00000000001 in accor-
dance with JEDEC publication 106-A.
Always a logic 1
Description
External Test
REG ID Code Inspection
Sample Boundary
Reserved
Bypass Scan