am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 75

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

SCSI Controller
The primary function of the PCnet-SCSI controller is to
transfer data between the 4 byte-wide PCI bus and 1
byte-wide SCSI bus. The controller consists of two
blocks: SCSI and DMA. The SCSI block sits between
the SCSI bus and the DMA block. It controls data flow
to/from SCSI bus. The DMA block is located between
the SCSI block and the PCI bus Interface Unit. It handles
data flow to/from PCI bus.
The operation of each block is governed by a set of con-
trol registers:
1. Channel Context Block (CCB) registers control the
2. SCSI registers control the SCSI block
In a normal operation, both sets of registers must be pro-
grammed with the specifics of the transfer, such as start-
ing address, transfer count, etc. (For more information,
refer to Technical Manual PID #18738A).
SCSI Specific DMA Engine
The SCSI Specific DMA Engine in the Am79C974 pro-
Since the PCI bus is 4 bytes wide and the SCSI bus is
only 1 byte wide, funneling logic is included in this en-
DMA block
Interface
Config
Space
PCI
Bus
Unit
PCI
PCI^REQ
PCI^GNT
Data
AD(4:0), CS
Figure 25. PCI BIU – DMA Engine – SCSI Block
C/BE(3:0)
32
AD (4:0)
Full
CNTL
DMA
(24x32)
DMA
REG
Path
Data
P R E L I M I N A R Y
Unit
FIFO
DMA
Am79C974
Empty
WR, RD ,
Funnel/Alignment
Data
32
DMA Engine
vides bus-mastering capabilities to allow flexibility and
performance advantages over slave PCI-SCSI devices.
Built into the engine is a 96-byte (24 DWORD) FIFO and
additional logic to handle the transition between the
32-bit PCI bus and the 8-bit SCSI bus.
Figure 25 illustrates the DMA Engine in relation to the
PCI interface and the SCSI block. As its most basic func-
tion, the DMA engine acts as the DMA controller in a bus
master capacity on the PCI bus, transferring data be-
tween memory and the SCSI block. All Command, Data,
Status, and Message bytes pass through the DMA FIFO
on their way to or from the SCSI bus. However, for pro-
grammed I/O (PIO) accesses to the SCSI registers, the
DMA FIFO is bypassed as data moves directly from the
SCSI block to the PCI interface. Since PIO operations
do not pass through the funneling logic and DMA FIFO,
data is transferred one byte at a time from the SCSI
block to the PCI interface via the least significant byte
lane. (The three most significant byte lanes will contain
null data.)
gine to handle byte alignment and to ensure that data is
properly transferred between the SCSI bus and the
Logic
8 Data
DREQ
DACK
16
Data
AD(3:0)
CS
RD
WR
SCSI Block
SCSI REG
(16x9)
SCSI
FIFO
18681A-29
AMD
75