am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 22

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

LED3
LED3
Output
This pin is shared with the EEDO function of the
Microwire serial EEPROM interface. When functioning
as LED3, the signal on this pin is programmable through
BCR7. By default, LED3 is active LOW and it indicates
transmit activity on the network. Special attention must
be given to the external circuitry attached to this pin. If
an LED circuit were directly attached to this pin, it would
create an I
serial EEPROM that would also be attached to this pin.
Therefore, if this pin is to be used as an additional LED
output while an EEPROM is used in the system, then
buffering is required between the LED3 pin and the LED
circuit. If no EEPROM is included in the system design,
then the LED3 signal may be directly connected to an
LED without buffering. The LED3 output from the
PCnet-SCSI controller is capable of sinking the 12 mA of
current necessary to drive an LED in this case. For more
details regarding LED connection, see the section on
LEDs.
LNKST
LINK Status
Output
This pin provides 12 mA for driving an LED. By default, it
indicates an active link connection on the 10BASE-T in-
terface. This pin can also be programmed to indicate
other network status (see BCR4). The LNKST pin
polarity is programmable, but by default, it is active
LOW. Note that this pin is multiplexed with the EEDI
function.
SLEEP
Sleep
Input
When SLEEP is asserted (active LOW), the PCnet-
SCSI controller performs an internal system reset of the
S_RESET type and then proceeds into a power savings
mode. (The reset operation caused by SLEEP assertion
will not affect BCR registers.) The PCI interface section
is not effected by SLEEP. In particular, access to the
PCI configuration space remains possible. None of the
configuration registers will be reset by SLEEP. All I/O
accesses to the PCnet-SCSI controller will result in a
PCI target abort response. The PCnet-SCSI controller
will not assert REQ while in sleep mode. When SLEEP
is asserted, all non-PCI interface outputs will be placed
in their normal S_RESET condition. All non-PCI inter-
face inputs will be ignored except for the SLEEP pin it-
self. De-assertion of SLEEP results in wake-up. The
system must refrain from starting the network opera-
tions of the PCnet-SCSI device for 0.5 seconds follow-
ing the deassertion of the SLEEP signal in order to allow
internal analog circuits to stabilize.
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requirement that could not be met by the
P R E L I M I N A R Y
Am79C974
Both CLK and XTAL1 inputs must have valid clock sig-
nals present in order for the SLEEP command to take
effect. If SLEEP is asserted while REQ is asserted, then
the PCnet-SCSI controller will wait for the assertion of
GNT. When GNT is asserted, the REQ signal will be de-
asserted and then the PCnet-SCSI controller will pro-
ceed to the power savings mode.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the asser-
tion of SLEEP until three CLK cycles after the comple-
tion of a valid pin RST operation.
The SLEEP pin does not affect the SCSI section.
XTAL1
Crystal Oscillator Input
Input
XTAL2
Crystal Oscillator Output
Output
The crystal frequency determines the network data rate.
The PCnet-SCSI controller supports the use of quartz
crystals to generate a 20 MHz frequency compatible
with the ISO 8802-3 (IEEE/ANSI 802.3) network fre-
quency tolerance and jitter specifications. See the sec-
tion External Crystal Characteristics (in section
Manchester Encoder/Decoder) for more detail.
The network data rate is one-half of the crystal fre-
quency. XTAL1 may alternatively be driven using an ex-
ternal CMOS level source, in which case XTAL2 must
be left unconnected. Note that when the PCnet-SCSI
controller is in coma mode, there is an internal 22 K re-
sistor from XTAL1 to ground. If an external source drives
XTAL1, some power will be consumed driving this resis-
tor. If XTAL1 is driven LOW at this time power consump-
tion will be minimized. In this case, XTAL1 must remain
active for at least 30 cycles after the assertion of SLEEP
and deassertion of REQ.
Microwire EEPROM Interface
EESK
EEPROM Serial Clock
Input/Output
The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the Microwire interface protocol. EESK is con-
nected to the Microwire EEPROM’s Clock pin. It is con-
trolled by either the PCnet-SCSI controller directly
during a read of the entire EEPROM, or indirectly by the
host system by writing to BCR19, bit 1.
The EESK pin is also used during EEPROM Auto-detec-
tion to determine whether or not an EEPROM is present