am79c974 Advanced Micro Devices, am79c974 Datasheet - Page 150

• Manufacturer Part Number: am79c974
• Description: Pcnettm-scsi Combination Ethernet And Scsi Controller For Pci Systems
• Manufacturer: Advanced Micro Devices

DMA Scatter-Gather Mechanism
The Am79C974 contains a scatter-gather translation
mechanism which facilitates faster data transfers. This
feature uses a Memory Descriptor List (a list of contigu-
ous physical memory addresses) which is stored in sys-
tem memory. Use of the Memory Descriptor List allows
a single SCSI transfer to be read from (or written to) non-
contiguous physical memory locations. This mecha-
nism avoids copying the transfer data and MDL list,
which was previously required for conventional DMA
operations.
Memory Descriptor List (MDL)
The MDL is a non-terminated (no End Of File marker)
list of 32-bit page frame addresses, which is always
aligned on a Double Word boundary. The format is
shown below:
31
16
Page Frame Address
AMD
31
31
SMDLA
WMAC
12 11
Ignored
A M E N D M E N T
0
0
Am79C974
0
DMA Scatter-Gather Operation
(4k aligned elements)
The scatter-gather mechanism described below
assumes 4k page alignment and size for all MDL entries
except the first and last entry. This feature is enabled by
setting the MDL bit in the DMA Command register (Bit 4,
Address (B)+40h).
1. a) Prepare the Memory Descriptor List (MDL)
Note: The value in the SMDLA register must be double
word aligned. Therefore, read/write transactions will al-
ways begin on a double word boundary.
31
b) Load the address of the starting entry in the
c) Program the Starting Transfer Count (STC)
Page Frame Address #1
Page Frame Address #2
Page Frame Address #3
Page Frame Address #4
Page Frame Address #n
through software and store it in system
memory.
Memory Descriptor List (MDL) into the Start
Memory Descriptor List Address (SMDLA)
register. This value is automatically copied into
the Working MDL Address Counter (WMAC).
register with the total transfer length (i.e., # of
bytes). Also program the Starting Physical
Address (SPA) register (bits 11:0) with the
starting offset of the first entry.
MDL
12
Ignored
Ignored
Ignored
Ignored
Ignored
18681A/1-31
0