zl50417 ETC-unknow, zl50417 Datasheet - Page 90

• Manufacturer Part Number: zl50417
• Description: Unmanaged 16-port 10/100m +2-port Ethernet Switch
• Manufacturer: ETC-unknow

90
ZL50417
C8
A9
B9
F4, F5, G4, G5, H4, H5,
J4, J5, K4, K5, L4, L5,
M4, M5, N4, N5, G3,
H1, H2, H3, J1, J2, J3,
K1, K2, K3, L1, L2, L3,
M1, M2, M3, U4, U5,
V4, V5, W4, W5, Y4,
Y5, AA4, AA5, AB4,
AB5, AC4, AC5, AD4,
AD5, W1, Y1, Y2, Y3,
AA1, AA2, AA3, AB1,
AB2, AB3, AC1, AC2,
AC3, AD1, AD2, AD3
N3, N2, N1, P3, P2, P1,
R5, R4, R3, R2, R1, T5,
T4, T3, T2, T1, W3, W2
V1
G1
V3
P4
P5
V2
U1
U2
Ball No(s)
LA_OE#
LA_OE0#
LA_OE1#
LB_D[63:0]
LB_A[20:3]
LB_ADSC#
LB_CLK
LB_WE#
LB_WE0#
LB_WE1#
LB_OE#
LB_OE0#
LB_OE1#
Symbol
Zarlink Semiconductor Inc.
Output with pull up
Output with pull up
Output with pull up
I/O-TS with pull up.
Output
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output with pull up
Output with pull up
I/O
Frame Bank A Read Chip
Select for one layer SRAM
application
Frame Bank A Read Chip
Select for lower layer of two
layers SRAM application
Frame Bank A Read Chip
Select for upper layer of two
layers SRAM application
Frame Bank B– Data Bit [63:0]
Frame Bank B – Address Bit
[20:3]
Frame Bank B Address Status
Control
Frame Bank B Clock Input
Frame Bank B Write Chip
Select for one layer SRAM
application
Frame Bank B Write Chip
Select for lower layer of two
layers SRAM application
Frame Bank B Write Chip
Select for upper layer of two
layers SRAM application
Frame Bank B Read Chip
Select for one layer SRAM
application
Frame Bank B Read Chip
Select for lower layer of two
layers SRAM application
Frame Bank B Read Chip
Select for upper layer of two
layers SRAM application
Description
Data Sheet