zl50417 ETC-unknow, zl50417 Datasheet - Page 18

• Manufacturer Part Number: zl50417
• Description: Unmanaged 16-port 10/100m +2-port Ethernet Switch
• Manufacturer: ETC-unknow

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transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the gigabit ports to map the 8 transmit
priorities into 4 multicast queues, the LSB are discarded.
During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one
logical queue. The older head of line of the two queues is forwarded first.
The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to
which the frame is destined.
4.0
4.1
The ZL50417 provides two 64-bit-wide SRAM banks, SRAM Bank A and SRAM Bank B, with a 64-bit bus
connected to each. Each DMA can read and write from both bank A and bank B. The following figure provides an
overview of the ZL50417 SRAM banks.
4.2
Because the bus for each bank is 64 bits wide, frames are broken into 8-byte granules, written to and read from
memory. The first 8-byte granule gets written to Bank A, the second 8-byte granule gets written to Bank B, and so
on in alternating fashion. When reading frames from memory, the same procedure is followed, first from A, then
from B, and so on.
The reading and writing from alternating memory banks can be performed with minimal waste of memory
bandwidth. What’s the worst case? For any speed port, in the worst case, a 1-byte-long EOF granule gets written
to Bank A. This means that a 7-byte segment of Bank A bandwidth is idle, and furthermore, the next 8-byte
segment of Bank B bandwidth is idle, because the first 8 bytes of the next frame will be written to Bank A, not B.
This scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the
interframe gap is 20 bytes.
ZL50417
Overview
Detailed Memory Information
Memory Interface
Figure 5 - ZL50417 SRAM Interface Block Diagram (DMAs for 10/1000 Ports Only)
SRAM Bank A
TXDMA
0-7
TXDMA
8-15
Zarlink Semiconductor Inc.
SRAM Bank B
RXDMA
0-7
RXDMA
8-15
Data Sheet