zl50417 ETC-unknow, zl50417 Datasheet - Page 49

• Manufacturer Part Number: zl50417
• Description: Unmanaged 16-port 10/100m +2-port Ethernet Switch
• Manufacturer: ETC-unknow

Data Sheet
13.2.3
CPU Address:h036
Accessed by CPU and serial interface (R/W)
Bit[0]:
Bit[1]:
Bit[2]:
Bit[3]:
GGControl – Extra GIGA Port Control
•
•
•
•
Reset GIGA port A
-
-
GIGA port A use MII interface (10/100M)
-
-
Reserved - Must be zero
GIGA port A direct flow control (MAC to MAC connection). The ZL50417 supports direct
flow control mechanism; the flow control frame is therefore not sent through the Gigabit
port data path.
-
-
•
•
•
•
•
•
0: Normal operation (default)
1: Reset Gigabit port A. Normally used when a new Phy is connected (Hot swap).
0: Gigabit port operations at 1000 mode (default)
1: Gigabit port operations at 10/100 mode
0: Direct flow control disabled (default)
1: Direct flow control enabled
A MAC address is defined as secure when its entry at MAC table has static
status and bit 0 is set to 1. MAC address bit 0 (the first bit transmitted)
indicates whether the address is unicast or multicast. As source addresses
are always unicast bit 0 is not used (always 0). ZL50417 uses this bit to
define secure MAC addresses.
If the port is set as learning disable and the source MAC address of the
incoming packet is not defined in the MAC address table.
If the port is configured to filter untagged frames and an untagged frame
arrives or if the port is configured to filter tagged frames and a tagged frame
arrives.
If the port is configured to filter untagged frames and an untagged frame
arrives or if the port is configured to filter tagged frames and a tagged frame
arrives.
If one of these three conditions occurs, the packet will be handled according
to one of the following specified options:
CPU installed
-
-
-
-
00 – Disable port security
01 – Discard violating packets
10 – Send packet to CPU and destination port
11 – Send packet to CPU only
7
DF
6
5
MiiB
Zarlink Semiconductor Inc.
4
RstA
3
DF
2
1
MiiA
0
RstA
ZL50417
49