zl50417 ETC-unknow, zl50417 Datasheet - Page 2

• Manufacturer Part Number: zl50417
• Description: Unmanaged 16-port 10/100m +2-port Ethernet Switch
• Manufacturer: ETC-unknow

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Description
The ZL50417 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip
provides 16 ports at 10/100 Mbps, 2 ports at 1000 Mbps. The Gigabit ports can also support 10/100M.
The chip supports up to 64K MAC addresses. The centralized shared memory architecture permits a very high
performance packet forwarding rate at up to 5.357M packets per second at full wire speed. The chip is optimized to
provide low-cost, high-performance workgroup switching.
Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate
bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously.
With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the
ZL50417 provides powerful QoS functions for various multimedia and mission-critical applications. The chip
provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is
assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged
frame, or the DS/TOS field, and UDP/TCP logical port fields in IP packets. The ZL50417 recognizes a total of 16
UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).
The ZL50417 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports, and
the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load sharing
can be used to group ports between interlinked switches to increase the effective network bandwidth.
In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long
activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50417 also supports a per-system
option to enable flow control for best effort frames, even on QoS-enabled ports.
The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to
SERDES chips. The PCS can be bypassed to provide a GMII interface.
The ZL50417 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are
capable of directly interfacing to LVTTL levels. The ZL50417 is packaged in a 553-pin Ball Grid Array package.
ZL50417
• User controls the WRED thresholds.
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID.
3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100
ports per group. Or 8 groups for 10/100 ports with up to 2 10/100 ports per group
Load sharing among trunked ports can be based on source MAC and/or destination MAC. The Gigabit
trunking group has one more option, based on source port.
Port Mirroring to a dedicated mirroring port
Full set of LED signals provided by a serial interface, or 6 LED signals dedicated to Gigabit port status only
(without serial interface)
Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports
Built-in reset logic triggered by system malfunction
Built-In Self Test for internal and external SRAM
I²C EEPROM for configuration
553 BGA package
Zarlink Semiconductor Inc.
Data Sheet