zl50408 Zarlink Semiconductor, zl50408 Datasheet - Page 71

• Manufacturer Part Number: zl50408
• Description: Managed 8-port 10/100m 1-port 10/100/1000m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

13.3.1.5
CPU Address:h036
Accessed by CPU (R/W)
13.3.1.6
CPU Address:h037
Accessed by CPU (R/W)
BUF_LIMIT – Frame Buffer Limit
FCC – Flow Control Grant Period
Bit [2]:
Bit [4:3]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [6:0]:
Bit [7]:
Bit [2:0]:
Bit [7:3]:
Internal loopback.
0: Disable (Default)
1: Enable
In this mode, the packet is looped back in the MAC layer before going out of the
chip. You must force linkup at full duplex as well.
External loopback is another level of system diagnostic which involves the PHY
device to loopback the packet.
Interface mode:
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Reserved
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
Frame Buffer Limit (max 4 KB). Multiple of 64 bytes (Default 0x40)
Reserved
00 - MII mode
11 - GMII mode (Default)
Flow Control Grant Period (Default 0x3)
Reserved
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ZL50408
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Data Sheet