zl50063 Zarlink Semiconductor, zl50063 Datasheet - Page 6

• Manufacturer Part Number: zl50063
• Description: 16k-channel Digital Switch With High Jitter Tolerance, Single Rate 32mbps , And 32 Inputs And 32 Output
• Manufacturer: Zarlink Semiconductor

Figure 1 - ZL50063 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50063 PBGA Connections (196 PBGA, 15mm x 15mm) Pin Diagram
Figure 3 - 16,384 x 16,384 Channels (32Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4 - 8,192 x 8,192 Channels (32Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6 - ST-BUS and GCI-Bus Input Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - Input and Output (Generated) Frame Pulse Alignment for Different Data Rates . . . . . . . . . . . . . . . . . 18
Figure 8 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 32Mbps. . . . . . . . . . . . . . . . . . 20
Figure 9 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of
Figure 10 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 32Mbps . . . . . . . . . . . 22
Figure 11 - Data Throughput Delay with Input Ch0 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch13. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13 - Data Throughput Delay with Input Ch13 Switched to Output Ch0. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14 - Hardware RESET De-assertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 19 - ST-BUS Local/Backplane Data Timing Diagram (32Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20 - GCI-Bus Local/Backplane Data Timing Diagram (32Mbps). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 21 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 22 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 23 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 24 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
32Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
List of Figures
Zarlink Semiconductor Inc.
ZL50063
6
Data Sheet