zl50063 Zarlink Semiconductor, zl50063 Datasheet - Page 25

• Manufacturer Part Number: zl50063
• Description: 16k-channel Digital Switch With High Jitter Tolerance, Single Rate 32mbps , And 32 Inputs And 32 Output
• Manufacturer: Zarlink Semiconductor

7.2
Upon power up, the device should be initialized by applying the following sequence:
7.3
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is
then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and
BORS, the output streams LSTo0-15 and BSTo0-15 are set to HIGH or high impedance, and all internal registers
and counters are reset to the default state.
The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A
delay of an additional 250 s must also be waited before the first microprocessor access is performed following
the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format.
In addition, the reset signal must be de-asserted less than 12 s after the frame boundary or more than 13 s after
the frame boundary, as illustrated in Figure 14. This can be achieved, for example, by synchronizing the
de-assertion of the reset signal with the input frame pulse FP8i.
1
2
3
4
5
(case 2)
Initialization
Reset
(case 1)
RESET
RESET
Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
Set ODE pin to LOW. This sets the LSTo0-15 outputs to HIGH or high impedance, dependent on the
LORS input value, and sets the BSTo0-15 outputs to HIGH or high impedance, dependent on BORS
input value. Refer to Pin Description for details of the LORS and BORS pins.
Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A
delay of an additional 250 s must also be applied before the first microprocessor access is
performed following the de-assertion of the RESET pin; this delay is required for determination of the
input frame pulse format.
Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to Section 8.3, Connection Memory Block Programming.
Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.
FP8i
RESET assertion
De-assertion of RESET must not fall within this window
12 s
13 s
Figure 14 - Hardware RESET De-assertion
RESET de-assertion
Zarlink Semiconductor Inc.
ZL50063
25
Data Sheet