zl50063 Zarlink Semiconductor, zl50063 Datasheet - Page 33

• Manufacturer Part Number: zl50063
• Description: 16k-channel Digital Switch With High Jitter Tolerance, Single Rate 32mbps , And 32 Inputs And 32 Output
• Manufacturer: Zarlink Semiconductor

Bit
1:0
10
9
8
7
6
5
4
3
2
Reserved
Reserved
Reserved
C8IPOL
COPOL
MS[1:0]
FBDEN
Name
FPW
MBP
OSB
Reset
Value
0
0
0
0
0
0
0
0
0
0
Frame Boundary Discriminator Enable
When LOW, the frame boundary discriminator function is disabled.
When HIGH, enables frame boundary discriminator function which allows the
device to tolerate inconsistent frame boundaries, hence improving the tolerance to
cycle-to-cycle variation on the input clock.
Reserved
Must be set to 0 for normal operation
Frame Pulse Width
When LOW, the user must apply a 122ns frame pulse on FP8i; the FP8o pin will
output a 122ns wide frame pulse; FP16o will output a 61ns wide frame pulse.
When HIGH, the user must apply a 244ns frame pulse on FP8i; the FP8o pin will
output a 244ns wide frame pulse; FP16o will output a 122ns wide frame pulse.
Reserved
Must be set to 0 for normal operation
8MHz Input Clock Polarity
The frame boundary is aligned to the falling or rising edge of the input clock.
When LOW, the frame boundary is aligned to the clock falling edge.
When HIGH, the frame boundary is aligned to the clock rising edge.
Output Clock Polarity
When LOW, the output clock has the same polarity as the input clock.
When HIGH, the output clock is inverted.
This applies to both the 8MHz (C8o) and 16MHz (C16o) output clocks.
Memory Block Programming
When LOW, the memory block programming mode is disabled.
When HIGH, the connection memory block programming mode is ready to program
the Local Connection Memory (LCM) and the Backplane Connection Memory
(BCM).
Output Stand By
This bit enables the BSTo0-15 and LSTo0-15 serial outputs.
When LOW, BSTo0-15 and LSTo0-15 are driven HIGH or high impedance,
dependent on the BORS and LORS pin settings respectively.
When HIGH, BSTo0-15 and LSTo0-15 are enabled.
Reserved
Must be set to 0 for normal operation
Memory Select Bits
These three bits select the connection or data memory for subsequent microport
memory access operations:
00 selects Local Connection Memory (LCM) for read or write operations.
01 selects Backplane Connection Memory (BCM) for read or write operations.
10 selects Local Data Memory (LDM) for read-only operation.
11 selects Backplane Data Memory (BDM) for read-only operation.
Output Control with ODE pin and OSB bit
Table 11 - Control Register Bits (continued)
ODE Pin
0
1
1
Zarlink Semiconductor Inc.
ZL50063
OSB bit
33
X
0
1
Description
BSTo0-15, LSTo0-15
Disabled
Disabled
Enabled
Data Sheet